erebion/coreboot
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we need cache_enable and disable visible.

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failed attempts to get the acer northbridge to size ram
CV:S ----------------------------------------------------------------------
This commit is contained in:
Ronald G. Minnich 2001-04-12 18:36:53 +00:00
commit 3a8ce19f87
2 changed files with 38 additions and 6 deletions
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4
src/cpu/p6/l2_cache.c
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@ -56,7 +56,7 @@ static int calculate_l2_cache_size(void);
static int calculate_l2_physical_address_range(void);
static int calculate_l2_ecc(void);
static void cache_disable(void)
void cache_disable(void)
{
unsigned int tmp;
@ -72,7 +72,7 @@ static void cache_disable(void)
: "=r" (tmp) : : "memory");
}
static void cache_enable(void)
void cache_enable(void)
{
unsigned int tmp;