From 3a5c1ae56a5944eddc3d73505746c899b40ac908 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Mon, 3 Mar 2025 15:15:23 +0100
Subject: [PATCH] Revert "soc/amd/glinda/cpu: Update smbios parameters"

This reverts commit 00b4a61dc53c68b47d1452c387409f2eadf32c93.

I have strong doubts that this is Glinda-specific, so this probably
should have been made common after verifying.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7fa0dca4c92f7bb0d49956aa9f1588b5fcba585
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86688
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/amd/glinda/cpu.c | 16 ----------------
 1 file changed, 16 deletions(-)

diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c
index 680b0957d3..26380077f2 100644
--- a/src/soc/amd/glinda/cpu.c
+++ b/src/soc/amd/glinda/cpu.c
@@ -17,22 +17,6 @@ unsigned int smbios_processor_external_clock(void)
 {
 	return 100; // 100 MHz
 }
-
-unsigned int smbios_cache_error_correction_type(u8 level)
-{
-	return SMBIOS_CACHE_ERROR_CORRECTION_MULTI_BIT;
-}
-
-unsigned int smbios_cache_conf_operation_mode(u8 level)
-{
-	return SMBIOS_CACHE_OP_MODE_WRITE_BACK;
-}
-
-unsigned int smbios_cache_sram_type(void)
-{
-	return SMBIOS_CACHE_SRAM_TYPE_PIPELINE_BURST;
-}
-
 static void zen_2_3_init(struct device *dev)
 {
 	check_mca();