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Clean up do_normal_boot() by adding defines, moving defines to the header file, and add a function header.

Browse source 
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@457 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Marc Jones 2007-07-18 19:19:48 +00:00
commit 396fdc33a7
2 changed files with 30 additions and 88 deletions
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111
arch/x86/mc146818rtc.c
View file

@ -2,6 +2,7 @@
*
* Copyright (C) 200X FIXME
* Copyright (C) 2007 coresystems GmbH
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -42,75 +43,6 @@ outb((addr),RTC_PORT(0)); \
outb((val),RTC_PORT(1)); \
})
/* control registers - Moto names
*/
#define RTC_REG_A 10
#define RTC_REG_B 11
#define RTC_REG_C 12
#define RTC_REG_D 13
/**********************************************************************
* register details
**********************************************************************/
#define RTC_FREQ_SELECT RTC_REG_A
/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus,
* reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
* totalling to a max high interval of 2.228 ms.
*/
# define RTC_UIP 0x80
# define RTC_DIV_CTL 0x70
/* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
# define RTC_REF_CLCK_4MHZ 0x00
# define RTC_REF_CLCK_1MHZ 0x10
# define RTC_REF_CLCK_32KHZ 0x20
/* 2 values for divider stage reset, others for "testing purposes only" */
# define RTC_DIV_RESET1 0x60
# define RTC_DIV_RESET2 0x70
/* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
# define RTC_RATE_SELECT 0x0F
# define RTC_RATE_NONE 0x00
# define RTC_RATE_32786HZ 0x01
# define RTC_RATE_16384HZ 0x02
# define RTC_RATE_8192HZ 0x03
# define RTC_RATE_4096HZ 0x04
# define RTC_RATE_2048HZ 0x05
# define RTC_RATE_1024HZ 0x06
# define RTC_RATE_512HZ 0x07
# define RTC_RATE_256HZ 0x08
# define RTC_RATE_128HZ 0x09
# define RTC_RATE_64HZ 0x0a
# define RTC_RATE_32HZ 0x0b
# define RTC_RATE_16HZ 0x0c
# define RTC_RATE_8HZ 0x0d
# define RTC_RATE_4HZ 0x0e
# define RTC_RATE_2HZ 0x0f
/**********************************************************************/
#define RTC_CONTROL RTC_REG_B
# define RTC_SET 0x80 /* disable updates for clock setting */
# define RTC_PIE 0x40 /* periodic interrupt enable */
# define RTC_AIE 0x20 /* alarm interrupt enable */
# define RTC_UIE 0x10 /* update-finished interrupt enable */
# define RTC_SQWE 0x08 /* enable square-wave output */
# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
/**********************************************************************/
#define RTC_INTR_FLAGS RTC_REG_C
/* caution - cleared by read */
# define RTC_IRQF 0x80 /* any of the following 3 is active */
# define RTC_PF 0x40
# define RTC_AF 0x20
# define RTC_UF 0x10
/**********************************************************************/
#define RTC_VALID RTC_REG_D
# define RTC_VRT 0x80 /* valid RAM and time */
/**********************************************************************/
#if defined(CONFIG_OPTION_TABLE) && (CONFIG_OPTION_TABLE == 1)
static int rtc_checksum_valid(int range_start, int range_end, int cks_loc)
@ -311,7 +243,7 @@ int get_option(void *dest, char *name)
static int cmos_error(void)
{
unsigned char reg_d;
u8 reg_d;
/* See if the cmos error condition has been flagged */
reg_d = CMOS_READ(RTC_REG_D);
return (reg_d & RTC_VRT) == 0;
@ -319,8 +251,8 @@ static int cmos_error(void)
static int cmos_chksum_valid(void)
{
unsigned char addr;
unsigned long sum, old_sum;
u8 addr;
u32 sum, old_sum;
sum = 0;
/* Comput the cmos checksum */
for(addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
@ -338,24 +270,29 @@ static int cmos_chksum_valid(void)
int last_boot_normal(void)
{
unsigned char byte;
u8 byte;
byte = CMOS_READ(RTC_BOOT_BYTE);
return (byte & (1 << 1));
return (byte & RTC_LAST_BOOT_FLAG_SET);
}
static int do_normal_boot(void)
/**
* Check CMOS for normal or fallback boot mode.
* Use lxbios to set normal mode once the system is operational.
*/
int do_normal_boot(void)
{
unsigned char byte;
u8 byte;
if (cmos_error() || !cmos_chksum_valid()) {
unsigned char byte;
/* There are no impossible values, no cheksums so just
* trust whatever value we have in the the cmos,
* but clear the fallback bit.
*/
byte = CMOS_READ(RTC_BOOT_BYTE);
byte &= 0x0c;
byte |= MAX_REBOOT_CNT << 4;
byte &= ~(0x0f << RTC_BOOT_COUNT_SHIFT
| RTC_LAST_BOOT_FLAG_SET | RTC_NORMAL_BOOT_FLAG_SET);
byte |= MAX_REBOOT_CNT << RTC_BOOT_COUNT_SHIFT;
CMOS_WRITE(byte, RTC_BOOT_BYTE);
}
@ -363,28 +300,28 @@ static int do_normal_boot(void)
byte = CMOS_READ(RTC_BOOT_BYTE);
/* Are we in normal mode? */
if (byte & 1) {
byte &= 0x0f; /* yes, clear the boot count */
if (byte & RTC_NORMAL_BOOT_FLAG_SET) {
byte &= ~(0x0f << RTC_BOOT_COUNT_SHIFT); /* yes, clear the boot count */
}
/* Properly set the last boot flag */
byte &= 0xfc;
byte &= ~(RTC_LAST_BOOT_FLAG_SET | RTC_NORMAL_BOOT_FLAG_SET);
if ((byte >> 4) < MAX_REBOOT_CNT) {
byte |= (1<<1);
byte |= RTC_LAST_BOOT_FLAG_SET;
}
/* Are we already at the max count? */
if ((byte >> 4) < MAX_REBOOT_CNT) {
byte += 1 << 4; /* No, add 1 to the count */
if ((byte >> RTC_BOOT_COUNT_SHIFT) < MAX_REBOOT_CNT) {
byte += 1 << RTC_BOOT_COUNT_SHIFT; /* No, add 1 to the count */
}
else {
byte &= 0xfc; /* Yes, put in fallback mode */
byte &= ~RTC_NORMAL_BOOT_FLAG_SET; /* Yes, put in fallback mode */
}
/* Save the boot byte */
CMOS_WRITE(byte, RTC_BOOT_BYTE);
return (byte & (1<<1));
return (byte & RTC_LAST_BOOT_FLAG_SET);
}

7
include/mc146818rtc.h
View file

@ -1,6 +1,7 @@
/*
* Copyright (C) 200X FIXME
* Copyright (C) 2007 coresystems GmbH
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -111,10 +112,14 @@
#define LB_CKS_LOC 126
#endif
#define RTC_BOOT_BYTE 48
#define RTC_BOOT_BYTE 48
#define RTC_BOOT_COUNT_SHIFT 4
#define RTC_LAST_BOOT_FLAG_SET (1<<1)
#define RTC_NORMAL_BOOT_FLAG_SET (1<<0)
void rtc_init(int invalid);
int get_option(void *dest, char *name);
int last_boot_normal(void);
int do_normal_boot(void);
#endif /* MC146818RTC_H */