From 394dfcaa7b162f28d7b0a92428d688ef59ac82cb Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Tue, 27 May 2025 14:12:52 -0700 Subject: [PATCH] mb/intel/ptlrvp: Handle GPIO support for DDR5 configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit addresses the GPIO configuration for DDR5 on Intel's PTLRVP mainboard. Specifically, it extends support for the DDR5 configuration by adding a case for PTLP_DDR5_RVP in the GPIO differential table function. This modification ensures proper handling of GPIO settings when DDR5 memory is configured, thereby improving system stability and compatibility. BUG=none TEST=Boot with DDR5 configuration. Change-Id: I3745c0a25e84a0f41dced44613cfd638c12fb1d3 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/87872 Reviewed-by: Jérémy Compostella Reviewed-by: Jamie Ryu Tested-by: build bot (Jenkins) Reviewed-by: Zhixing Ma --- src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c index 7b4dbe3c9f..7dcf6d7873 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c @@ -461,6 +461,7 @@ const struct pad_config *variant_board_gpio_diff_table(size_t *num) return t4_gpio_diff_table; case GCS_32GB: case GCS_64GB: + case PTLP_DDR5_RVP: return NULL; default: die("Unknown board ID = 0x%x\n", board_id);