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google/fizz: Enable cr50 over SPI

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We are changing the bootstraps in the EVTs so that the SOC
communicates with cr50 over SPI instead of cr50.  SPI is more reliable
than I2C.  Thus, disabling cr50 over I2C and enabling cr50 over SPI.

BUG=b:65056998, b:62456589
BRANCH=None
TEST=make sure that we can boot into kernel
     run cold_reset and warm_reset and make sure both
     boot successfully.
CQ-DEPEND=CL:714237

Change-Id: I85b9a61f0305e3c7ccada79d7702234a285a6d2a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/21970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Shelley Chen 2017-10-11 15:39:08 -07:00 • committed by Furquan Shaikh
commit 3918887c18
1 changed files with 1 additions and 1 deletions
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src/mainboard/google/fizz/Kconfig
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@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_USES_FSP2_0
select NO_FADT_8042
select SOC_INTEL_KABYLAKE
select FIZZ_USE_I2C_TPM
select FIZZ_USE_SPI_TPM
select GENERIC_SPD_BIN
select RT8168_GET_MAC_FROM_VPD