From 38cea98d93accc0d5d49842bfbdde0fb43b4fe2a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 27 Mar 2017 19:00:24 +0300 Subject: [PATCH] UPSTREAM: AGESA f14: Fix MemContext buffer parser for AmdInitPost() Memory training data that is saved as part of S3 feature in SPI flash can be used to bypass training on normal boot path as well. When RegisterSize is 3 in the register playback tables, no register is saved or restored. Instead a function is called to do certain things in the save and resume sequence. Previously, this was overlooked, and the pointer containing the current OrMask was still incremented by 3 bytes. BUG=none BRANCH=none TEST=none Change-Id: Ifeca0a8ab69209a4ce9c78cbdc97c82563a5f5ee Signed-off-by: Patrick Georgi Original-Commit-Id: c91ab1cfce1558a434dcc501ec57922928dafac0 Original-Change-Id: I7221a03d5a4e442817911ba4862e3c0e8fa4a500 Original-Signed-off-by: Kysti Mlkki Original-Reviewed-on: https://review.coreboot.org/19041 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/471462 --- .../amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c index 97320d9930..ee14fed847 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c @@ -347,7 +347,9 @@ MemMRestoreDqsTimings ( if (!MemMSetCSRNb (&NBArray[Node], Reg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & Reg->RegisterList[j].AndMask)) { return FALSE; // Restore fails } - OrMask += (Reg->RegisterList[j].Type.RegisterSize == 0) ? 4 : Reg->RegisterList[j].Type.RegisterSize; + if (Reg->RegisterList[j].Type.RegisterSize != 3) + OrMask += (Reg->RegisterList[j].Type.RegisterSize == 0) ? 4 : + Reg->RegisterList[j].Type.RegisterSize; } if (MaxNode < Node) { @@ -370,7 +372,9 @@ MemMRestoreDqsTimings ( if (!MemMSetCSRNb (&NBArray[Node], CReg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & CReg->RegisterList[j].AndMask)) { return FALSE; // Restore fails } - OrMask += (CReg->RegisterList[j].Type.RegisterSize == 0) ? 4 : CReg->RegisterList[j].Type.RegisterSize; + if (CReg->RegisterList[j].Type.RegisterSize != 3) + OrMask += (CReg->RegisterList[j].Type.RegisterSize == 0) ? 4 : + CReg->RegisterList[j].Type.RegisterSize; } } } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR_PRE_ESR)) || @@ -606,4 +610,4 @@ MemMCreateS3NbBlock ( } } } -} \ No newline at end of file +}