From 386feb720ebec01bba029d4bc1f906455111d839 Mon Sep 17 00:00:00 2001
From: Jason Chen <jason-ch.chen@mediatek.corp-partner.google.com>
Date: Fri, 3 Oct 2025 09:16:36 +0800
Subject: [PATCH] soc/mediatek/mt8196: Add DVFS support for the second SoC SKU

Devices utilizing the second SKU of the SoC experience system hangs due
to missing DVFS support. This patch adds DVFS support for the second
SKU to resolve this issue.

BRANCH=rauru
BUG=b:443664123
TEST=verify booting on both original and second SoC SKUs

Change-Id: If17ecd4a8358e08a45c4662bb92138b7a939512e
Signed-off-by: Jason Chen <jason-ch.chen@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89405
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: jason-ch chen <Jason-ch.Chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8196/dvfs.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/soc/mediatek/mt8196/dvfs.c b/src/soc/mediatek/mt8196/dvfs.c
index 255f95e4d9..6f609e4698 100644
--- a/src/soc/mediatek/mt8196/dvfs.c
+++ b/src/soc/mediatek/mt8196/dvfs.c
@@ -7,8 +7,12 @@
 void dvfs_init(void)
 {
 	uint32_t val;
+	uint32_t seg = read32p(EFUSEC_BASE + 0x50);
 
-	val = BIT(8) | BIT(0);
+	if (seg == 0x14)
+		val = BIT(9) | BIT(0);
+	else
+		val = BIT(8) | BIT(0);
 
 	write32p(CSRAM_BASE + 0x8, 0x55AA55AA);
 	write32p(CSRAM_BASE + 0xC, val);