From 36805eedcaabd7e7707b4dc34d7a91d31c993163 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Fri, 11 Apr 2025 09:22:34 +0300 Subject: [PATCH] superio/fintek/f81866d: Fix HWM port address The HWM port is +5 to the base address stored in LDN 0x4 at index 0x60/0x61. Take this rule into account when configuring the monitor, as it was done for Fintek SIO chips in the superiotool utility [1]. [1] commit d92745b TEST=Run coreboot on the motherboard with the Fintek F81966 chip (which is architecturally compatible) with pnp_write_hwm5_index() in the HWM initialization code: - the fans are regulated correctly; - superiotool prints the values of the configuration registers updated during initialization. Change-Id: If39400e56a7d0792a5bc8f312c29dd5e98a0b2d3 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/87273 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Harrie Paijmans --- src/superio/fintek/f81866d/f81866d_hwm.c | 32 ++++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c index a82adb3472..2883c02e96 100644 --- a/src/superio/fintek/f81866d/f81866d_hwm.c +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -51,34 +51,34 @@ void f81866d_hwm_init(struct device *dev) pnp_enter_conf_mode(dev); /* Use AMD TSI */ - pnp_write_index(port, HWM_AMD_TSI_ADDR, reg->hwm_amd_tsi_addr); - pnp_write_index(port, HWM_AMD_TSI_CONTROL_REG, reg->hwm_amd_tsi_control); + pnp_write_hwm5_index(port, HWM_AMD_TSI_ADDR, reg->hwm_amd_tsi_addr); + pnp_write_hwm5_index(port, HWM_AMD_TSI_CONTROL_REG, reg->hwm_amd_tsi_control); /* Set temp1 sensor to thermistor */ - pnp_write_index(port, TEMP_SENS_TYPE_REG, reg->hwm_temp_sens_type); + pnp_write_hwm5_index(port, TEMP_SENS_TYPE_REG, reg->hwm_temp_sens_type); /* Select FAN Type */ - pnp_write_index(port, HWM_FAN_SEL, reg->hwm_fan_select); + pnp_write_hwm5_index(port, HWM_FAN_SEL, reg->hwm_fan_select); /* Select FAN Mode*/ - pnp_write_index(port, HWM_FAN_MODE, reg->hwm_fan_mode); + pnp_write_hwm5_index(port, HWM_FAN_MODE, reg->hwm_fan_mode); /* Set Boundaries */ - pnp_write_index(port, HWM_FAN2_BOUND1, reg->hwm_fan2_bound1); - pnp_write_index(port, HWM_FAN2_BOUND2, reg->hwm_fan2_bound2); - pnp_write_index(port, HWM_FAN2_BOUND3, reg->hwm_fan2_bound3); - pnp_write_index(port, HWM_FAN2_BOUND4, reg->hwm_fan2_bound4); + pnp_write_hwm5_index(port, HWM_FAN2_BOUND1, reg->hwm_fan2_bound1); + pnp_write_hwm5_index(port, HWM_FAN2_BOUND2, reg->hwm_fan2_bound2); + pnp_write_hwm5_index(port, HWM_FAN2_BOUND3, reg->hwm_fan2_bound3); + pnp_write_hwm5_index(port, HWM_FAN2_BOUND4, reg->hwm_fan2_bound4); /* Set Speed */ - pnp_write_index(port, HWM_FAN2_SEG1_SPEED_COUNT, reg->hwm_fan2_seg1_speed); - pnp_write_index(port, HWM_FAN2_SEG2_SPEED_COUNT, reg->hwm_fan2_seg2_speed); - pnp_write_index(port, HWM_FAN2_SEG3_SPEED_COUNT, reg->hwm_fan2_seg3_speed); - pnp_write_index(port, HWM_FAN2_SEG4_SPEED_COUNT, reg->hwm_fan2_seg4_speed); - pnp_write_index(port, HWM_FAN2_SEG5_SPEED_COUNT, reg->hwm_fan2_seg5_speed); + pnp_write_hwm5_index(port, HWM_FAN2_SEG1_SPEED_COUNT, reg->hwm_fan2_seg1_speed); + pnp_write_hwm5_index(port, HWM_FAN2_SEG2_SPEED_COUNT, reg->hwm_fan2_seg2_speed); + pnp_write_hwm5_index(port, HWM_FAN2_SEG3_SPEED_COUNT, reg->hwm_fan2_seg3_speed); + pnp_write_hwm5_index(port, HWM_FAN2_SEG4_SPEED_COUNT, reg->hwm_fan2_seg4_speed); + pnp_write_hwm5_index(port, HWM_FAN2_SEG5_SPEED_COUNT, reg->hwm_fan2_seg5_speed); /* Set Fan control freq */ - pnp_write_index(port, HWM_FAN3_CONTROL, reg->hwm_fan3_control); - pnp_write_index(port, HWM_FAN2_TEMP_MAP_SEL, reg->hwm_fan2_temp_map_select); + pnp_write_hwm5_index(port, HWM_FAN3_CONTROL, reg->hwm_fan3_control); + pnp_write_hwm5_index(port, HWM_FAN2_TEMP_MAP_SEL, reg->hwm_fan2_temp_map_select); pnp_exit_conf_mode(dev); }