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tree: Replace And(a,b,c) with ASL 2.0 syntax

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Replace `And (a, b, c)` with `c = a & b`, respectively `c &= b` where
possible.

Change-Id: Ie558f9d0b597c56ca3b31498edb68de8877d3a2f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70850
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2022-12-16 07:11:17 +01:00
commit 35e65a8bc3
21 changed files with 60 additions and 60 deletions
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2
src/soc/intel/baytrail/acpi/lpe.asl
View file

@ -93,7 +93,7 @@ Device (LPEA)
Method (_ON)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}

20
src/soc/intel/baytrail/acpi/lpss.asl
View file

@ -118,7 +118,7 @@ Device (I2C1)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -177,7 +177,7 @@ Device (I2C2)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -236,7 +236,7 @@ Device (I2C3)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -295,7 +295,7 @@ Device (I2C4)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -354,7 +354,7 @@ Device (I2C5)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -413,7 +413,7 @@ Device (I2C6)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -472,7 +472,7 @@ Device (I2C7)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -525,7 +525,7 @@ Device (SPI1)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -634,7 +634,7 @@ Device (UAR1)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -687,7 +687,7 @@ Device (UAR2)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}

6
src/soc/intel/baytrail/acpi/scc.asl
View file

@ -47,7 +47,7 @@ Device (EMMC)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
@ -110,7 +110,7 @@ Device (SDIO)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -162,7 +162,7 @@ Device (SDCD)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}

2
src/soc/intel/braswell/acpi/lpe.asl
View file

@ -93,7 +93,7 @@ Device (LPEA)
Method (_ON)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}

18
src/soc/intel/braswell/acpi/lpss.asl
View file

@ -149,7 +149,7 @@ Device (I2C1)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -208,7 +208,7 @@ Device (I2C2)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -267,7 +267,7 @@ Device (I2C3)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -326,7 +326,7 @@ Device (I2C4)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -385,7 +385,7 @@ Device (I2C5)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -444,7 +444,7 @@ Device (I2C6)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -503,7 +503,7 @@ Device (I2C7)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -556,7 +556,7 @@ Device (UAR1)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -609,7 +609,7 @@ Device (UAR2)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}

6
src/soc/intel/braswell/acpi/scc.asl
View file

@ -47,7 +47,7 @@ Device (EMMC)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
@ -148,7 +148,7 @@ Device (SDIO)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -200,7 +200,7 @@ Device (SDCD)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}

4
src/soc/intel/cannonlake/acpi/scs.asl
View file

@ -45,7 +45,7 @@ Scope (\_SB.PCI0) {
^^SCSC (PID_EMMC)
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)
PMCR &= 0xFFFC
^TEMP = PMCR
}
@ -209,7 +209,7 @@ Scope (\_SB.PCI0) {
^^SCSC (PID_SDX)
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)
PMCR &= 0xFFFC
^TEMP = PMCR
#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE)

4
src/soc/intel/icelake/acpi/scs.asl
View file

@ -43,7 +43,7 @@ Scope (\_SB.PCI0) {
^^SCSC (PID_EMMC)
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)
PMCR &= 0xFFFC
^TEMP = PMCR
}
@ -96,7 +96,7 @@ Scope (\_SB.PCI0) {
^^SCSC (PID_SDX)
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)
PMCR &= 0xFFFC
^TEMP = PMCR
}