From 359ae676686bae6d7eae127ac5a769906ba7e50c Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Fri, 16 May 2025 01:46:58 -0700 Subject: [PATCH] elog: Handle elog in later boot phase Use POSTPONE_SPI_ACCESS to handle elog data later boot phase to avoid flash access delay by other boot controllers. Intel has pre-CPU boot controllers (e.g. CSE) which load non-CPU firmwares. Boot-critical firmwares are loaded before CPU reset and non-boot-critical firmwares are loaded during CPU boot. If another controller accesses SPI to load firmwares, reading SPI by CPU is ok, but writing to SPI for saving elog data can take ~32ms sometimes. Saving elog data usually takes less than 1ms. There are three elog handling sequences that need to move together under the Kconfig: - Soc folder - Elog driver folder - ChromeOS folder Before this change, sometimes it delays like below: BS: callback (0x7386d428) @ src/soc/intel/pantherlake/elog.c:216 (32 ms) After this change, the delay is less than 1 ms: BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms) TEST 1. Enable DEBUG_BOOT_STATE 2. Check time BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms)) Change-Id: I3f5e7acf5204e213179664d0d77151d415d00896 Signed-off-by: Wonkyu Kim Reviewed-on: https://review.coreboot.org/c/coreboot/+/87740 Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal --- src/drivers/elog/elog.c | 5 +++++ src/soc/intel/pantherlake/elog.c | 4 ++++ src/vendorcode/google/chromeos/elog.c | 4 ++++ 3 files changed, 13 insertions(+) diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index ecee145e31..54674ce9fb 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -898,4 +898,9 @@ int elog_add_extended_event(u8 type, u32 complement) /* Make sure elog_init() runs at least once to log System Boot event. */ static void elog_bs_init(void *unused) { elog_init(); } + +#if CONFIG(POSTPONE_SPI_ACCESS) +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, elog_bs_init, NULL); +#else BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, elog_bs_init, NULL); +#endif diff --git a/src/soc/intel/pantherlake/elog.c b/src/soc/intel/pantherlake/elog.c index 5abf766fc7..e5a6a9a3cf 100644 --- a/src/soc/intel/pantherlake/elog.c +++ b/src/soc/intel/pantherlake/elog.c @@ -210,7 +210,11 @@ static void pch_log_state(void *unused) pch_log_wake_source(ps); } +#if CONFIG(POSTPONE_SPI_ACCESS) +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, pch_log_state, NULL); +#else BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL); +#endif void elog_gsmi_cb_platform_log_wake_source(void) { diff --git a/src/vendorcode/google/chromeos/elog.c b/src/vendorcode/google/chromeos/elog.c index e60cec83b0..5dabb3cf7f 100644 --- a/src/vendorcode/google/chromeos/elog.c +++ b/src/vendorcode/google/chromeos/elog.c @@ -31,4 +31,8 @@ static void elog_add_vboot_info(void *unused) elog_add_event_raw(ELOG_TYPE_FW_VBOOT_INFO, &data, width); } +#if CONFIG(POSTPONE_SPI_ACCESS) +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, elog_add_vboot_info, NULL); +#else BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, elog_add_vboot_info, NULL); +#endif