diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index be44a9eabb..30be64a3e9 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -85,6 +85,7 @@ config SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk
index 5d604a994a..83ae0a8c14 100644
--- a/src/soc/intel/alderlake/Makefile.mk
+++ b/src/soc/intel/alderlake/Makefile.mk
@@ -10,12 +10,10 @@ all-y += pmutil.c
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
-bootblock-y += espi.c
 bootblock-y += p2sb.c
 bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c
 
 romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c
-romstage-y += espi.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
 romstage-y += reset.c
@@ -24,7 +22,6 @@ ramstage-y += acpi.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
 ramstage-y += elog.c
-ramstage-y += espi.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += graphics.c
diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c
deleted file mode 100644
index bdc41a6a30..0000000000
--- a/src/soc/intel/alderlake/espi.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * This file is created based on Intel Alder Lake Processor PCH Datasheet
- * Document number: 621483
- * Chapter number: 2
- */
-
-#include <device/pci.h>
-#include <pc80/isa-dma.h>
-#include <pc80/i8259.h>
-#include <arch/ioapic.h>
-#include <intelblocks/itss.h>
-#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
-#include <intelpch/espi.h>
-#include <soc/iomap.h>
-#include <soc/irq.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-#include <soc/soc_chip.h>
-#include <static.h>
-
-void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
-{
-	const config_t *config = config_of_soc();
-
-	gen_io_dec[0] = config->gen1_dec;
-	gen_io_dec[1] = config->gen2_dec;
-	gen_io_dec[2] = config->gen3_dec;
-	gen_io_dec[3] = config->gen4_dec;
-}
-
-#if ENV_RAMSTAGE
-void lpc_soc_init(struct device *dev)
-{
-	/* Legacy initialization */
-	isa_dma_init();
-	pch_misc_init();
-
-	/* Enable CLKRUN_EN for power gating ESPI */
-	lpc_enable_pci_clk_cntl();
-
-	/* Set ESPI Serial IRQ mode */
-	if (CONFIG(SERIRQ_CONTINUOUS_MODE))
-		lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
-	else
-		lpc_set_serirq_mode(SERIRQ_QUIET);
-
-	/* Interrupt configuration */
-	pch_enable_ioapic();
-	pch_pirq_init();
-	setup_i8259();
-	i8259_configure_irq_trigger(9, 1);
-}
-#endif