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google/oak: Increase the driving strength for 4GB DRAMs

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Some PVT units encountered DRAM calibration failure during
power on/off tests. The failure is caused by higher impedance
of the DRAM on those units. So increase the driving strength
for 4GB DRAMs.

BUG=chrome-os-partner:57392
TEST=run cold reboot 100 times on PVT units which have DRAM
calibration issue.

Change-Id: I8a329093db3f1def566e4b7afec3c4f4bfe44c6a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf1aa5ade8
Original-Change-Id: I0d1776cd1a5892d1f82e9bf414620d1ef6d29132
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/394451
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Pin-Huan Hsu <ph.hsu@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/16917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
PH Hsu 2016-10-06 12:31:52 +08:00 • committed by Patrick Georgi
commit 34a6537512
3 changed files with 6 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EB-4GB.inc
View file

@ -1,7 +1,7 @@
{ /* 4GB (16Gb + 16Gb) for dual rank dram setting */
{
.impedance_drvp = 0x9,
.impedance_drvn = 0xa,
.impedance_drvp = 0xc,
.impedance_drvn = 0xd,
.datlat_ucfirst = 19,
.ca_train = {

4
src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EE-4GB.inc
View file

@ -1,7 +1,7 @@
{ /* 4GB (16Gb + 16Gb) for dual rank dram setting */
{
.impedance_drvp = 0x9,
.impedance_drvn = 0xa,
.impedance_drvp = 0xc,
.impedance_drvn = 0xd,
.datlat_ucfirst = 18,
.ca_train = {

4
src/mainboard/google/oak/sdram_inf/sdram-lpddr3-hynix-4GB.inc
View file

@ -1,7 +1,7 @@
{ /* 2GB (8Gb + 8Gb) for single rank dram setting */
{
.impedance_drvp = 0x9,
.impedance_drvn = 0xa,
.impedance_drvp = 0xc,
.impedance_drvn = 0xd,
.datlat_ucfirst = 19,
.ca_train = {