diff --git a/northbridge/amd/k8/coherent_ht.c b/northbridge/amd/k8/coherent_ht.c
index 56437d6de2..3fbae88525 100644
--- a/northbridge/amd/k8/coherent_ht.c
+++ b/northbridge/amd/k8/coherent_ht.c
@@ -1503,12 +1503,7 @@ unsigned setup_smp(void)
 		nodes = setup_smp8();
 #endif
 
-#if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("%02x nodes initialized.\r\n", nodes);
-#else
-	print_debug_hex8(nodes);
-	print_debug(" nodes initialized.\r\n");
-#endif
+	printk(BIOS_DEBUG,"%02x nodes initialized.\r\n", nodes);
 	
 	return nodes;
 }
diff --git a/northbridge/amd/k8/domain.c b/northbridge/amd/k8/domain.c
index 2579a0a534..29cc5e45e8 100644
--- a/northbridge/amd/k8/domain.c
+++ b/northbridge/amd/k8/domain.c
@@ -259,7 +259,7 @@ static void k8_pci_domain_set_resources(struct device * dev)
 
 #if 1
 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
-	/* Round the mmio hold to 64M */
+	/* Round the mmio hole to 64M */
 	mmio_basek &= ~((64*1024) - 1);
 #endif
 
diff --git a/southbridge/amd/sb600/stage1_smbus.c b/southbridge/amd/sb600/stage1_smbus.c
index 57f399f60f..ac5f7f20e2 100644
--- a/southbridge/amd/sb600/stage1_smbus.c
+++ b/southbridge/amd/sb600/stage1_smbus.c
@@ -196,7 +196,7 @@ void alink_ab_indx(unsigned int reg_space, unsigned int reg_addr,
 	tmp &= ~mask;
 	tmp |= val;
 
-	/* printk_debug("about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
+	/* printk(BIOS_DEBUG,"about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
 	outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
 	outl(tmp, AB_DATA);
 }
diff --git a/southbridge/nvidia/mcp55/mcp55.c b/southbridge/nvidia/mcp55/mcp55.c
index ed679f5bcb..fc930b74b4 100644
--- a/southbridge/nvidia/mcp55/mcp55.c
+++ b/southbridge/nvidia/mcp55/mcp55.c
@@ -224,7 +224,7 @@ static void mcp55_enable(struct device *dev)
 //		reg |= (1<<0);
 		reg &= ~(0x3f<<4);
 		if (reg != reg_old) {
-			printk_debug("mcp55.c pcie enabled\n");
+			printk(BIOS_DEBUG,"mcp55.c pcie enabled\n");
 			pci_write_config32(sm_dev, 0xe4, reg);
 		}
 #endif