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AGESA,binaryPI: Add compatibility wrapper for romstage entry

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This simplifies transition and reviews towards C environment
bootblock by allowing single cache_as_ram.S file to be used.

Change-Id: I231972982e5ca6d0c08437693edf926b0eaf9ee1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37352
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-11-29 06:38:46 +02:00
commit 33d0fb8d34
4 changed files with 30 additions and 26 deletions
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3
src/include/bootblock_common.h
View file

@ -38,6 +38,9 @@ void bootblock_soc_init(void);
asmlinkage void bootblock_c_entry(uint64_t base_timestamp);
asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist);
/* To be used when APs execute through bootblock too. */
asmlinkage void ap_bootblock_c_entry(void);
void bootblock_main_with_basetime(uint64_t base_timestamp);
/* This is the argument structure passed from decompressor to bootblock. */

9
src/include/cpu/amd/car.h
View file

@ -1,9 +0,0 @@
#ifndef _CPU_AMD_CAR_H
#define _CPU_AMD_CAR_H
#include <arch/cpu.h>
asmlinkage void romstage_main(unsigned long bist);
asmlinkage void ap_romstage_main(void);
#endif