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UPSTREAM: soc/intel/apollolake: fix system reset eventlog

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The SRS bit which is supposed to indicate reset button press
is non-functional. If it did work the system reset event it
was associated with is overly specific. Therefore, use the
warm reset status bit.

BUG=b:37687843

Change-Id: I60636f2ec24e4255a718fa3c087a55006411def2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: f39692ee3e
Original-Change-Id: I34dd09c03d2bca72da9a5cdf23121e0d0e621fa6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19484
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490676
This commit is contained in:
Aaron Durbin 2017-04-27 14:14:05 -05:00 • committed by chrome-bot
commit 337dfb1d9d
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/apollolake/elog.c
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@ -73,7 +73,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
elog_add_event(ELOG_TYPE_RTC_RESET);
/* System Reset */
if (ps->gen_pmcon1 & SRS)
if (ps->gen_pmcon1 & WARM_RESET_STS)
elog_add_event(ELOG_TYPE_SYSTEM_RESET);
/* TCO Timeout */