diff --git a/configs/config.nyan b/configs/config.nyan
index 632ca0e261..2f1548407b 100644
--- a/configs/config.nyan
+++ b/configs/config.nyan
@@ -3,4 +3,6 @@ CONFIG_BOARD_GOOGLE_NYAN=y
 CONFIG_COREBOOT_ROMSIZE_KB_1024=y
 # CONFIG_CONSOLE_SERIAL is not set
 CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_PRERAM_BUFFER_SIZE=0x1fe0
 CONFIG_VBOOT_VERIFY_FIRMWARE=y
diff --git a/configs/config.nyan_big b/configs/config.nyan_big
index f0aec3a63f..19dbeabe91 100644
--- a/configs/config.nyan_big
+++ b/configs/config.nyan_big
@@ -3,4 +3,6 @@ CONFIG_BOARD_GOOGLE_NYAN_BIG=y
 CONFIG_COREBOOT_ROMSIZE_KB_1024=y
 # CONFIG_CONSOLE_SERIAL is not set
 CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_PRERAM_BUFFER_SIZE=0x1fe0
 CONFIG_VBOOT_VERIFY_FIRMWARE=y
diff --git a/configs/config.nyan_blaze b/configs/config.nyan_blaze
index dfd7c72ea2..8bf25b9467 100644
--- a/configs/config.nyan_blaze
+++ b/configs/config.nyan_blaze
@@ -3,4 +3,6 @@ CONFIG_BOARD_GOOGLE_NYAN_BLAZE=y
 CONFIG_COREBOOT_ROMSIZE_KB_1024=y
 # CONFIG_CONSOLE_SERIAL is not set
 CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_PRERAM_BUFFER_SIZE=0x1fe0
 CONFIG_VBOOT_VERIFY_FIRMWARE=y
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index 10aeb5466c..cc1bfae95c 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -25,6 +25,7 @@
 #include <device/device.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <console/cbmem_console.h>
 #include <console/console.h>
 #include <romstage_handoff.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -215,6 +216,9 @@ static void __attribute__((noinline)) romstage(void)
 				      "fallback/coreboot_ram");
 	timestamp_add(TS_END_COPYRAM, timestamp_get());
 
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_reinit();
+#endif
 	stage_exit(entry);
 }
 
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index c239b4eb7e..48d3842aa2 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -25,6 +25,7 @@
 #include <device/device.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <console/cbmem_console.h>
 #include <console/console.h>
 #include <romstage_handoff.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -215,6 +216,9 @@ static void __attribute__((noinline)) romstage(void)
 				      "fallback/coreboot_ram");
 	timestamp_add(TS_END_COPYRAM, timestamp_get());
 
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_reinit();
+#endif
 	stage_exit(entry);
 }
 
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c
index c239b4eb7e..48d3842aa2 100644
--- a/src/mainboard/google/nyan_blaze/romstage.c
+++ b/src/mainboard/google/nyan_blaze/romstage.c
@@ -25,6 +25,7 @@
 #include <device/device.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <console/cbmem_console.h>
 #include <console/console.h>
 #include <romstage_handoff.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -215,6 +216,9 @@ static void __attribute__((noinline)) romstage(void)
 				      "fallback/coreboot_ram");
 	timestamp_add(TS_END_COPYRAM, timestamp_get());
 
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_reinit();
+#endif
 	stage_exit(entry);
 }
 
diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig
index 267e287ae8..b3bad168ba 100644
--- a/src/soc/nvidia/tegra124/Kconfig
+++ b/src/soc/nvidia/tegra124/Kconfig
@@ -35,7 +35,8 @@ config BOOTBLOCK_CPU_INIT
 #  handoff that area may be reclaimed for other uses, e.g. CBFS cache.)
 #
 # 0x4000_0000 TTB (16K+32B). 32B is for L1 table of LPAE.
-# 0x4000_4020 CBFS mapping cache (96K-32B)
+# 0x4000_4020 CBMEM console area (8K-32B)
+# 0x4000_6000 CBFS mapping cache (88K)
 # 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!).
 # 0x4002_0000 Bootblock (max 48KB).
 # 0x4002_C000 ROM stage (max 80KB).
@@ -89,11 +90,15 @@ config TTB_BUFFER
 
 config CBFS_CACHE_ADDRESS
 	hex "memory address to put CBFS cache data"
-	default 0x40004020
+	default 0x40006000
 
 config CBFS_CACHE_SIZE
 	hex "size of CBFS cache data"
-	default 0x00017fe0
+	default 0x00016000
+
+config CBMEM_CONSOLE_PRERAM_BASE
+	hex "memory address of the CBMEM console buffer"
+	default 0x40004020
 
 choice CONSOLE_SERIAL_TEGRA124_UART_CHOICES
 	prompt "Serial Console UART"