From 32dd9947a60298ff9488c911629802c257ed6afc Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Mon, 4 Nov 2013 17:39:16 -0800 Subject: [PATCH] nyan: move clock setup for the display out of dca_init We can use the mainboard clock startup for this. This is Step 1. I'm doing this in pieces so bisect is easy if needed. BUG=None TEST=build and boot and see dev mode graphics BRANCH=None Change-Id: Id6d5a06b550c44c983aed42c639145cf46e301ce Signed-off-by: Ronald G. Minnich Reviewed-on: https://chromium-review.googlesource.com/175656 Reviewed-by: Julius Werner Commit-Queue: Ronald Minnich Tested-by: Ronald Minnich --- src/mainboard/google/nyan/mainboard.c | 10 +++++----- src/soc/nvidia/tegra124/clock.c | 3 ++- src/soc/nvidia/tegra124/displayhack.c | 20 -------------------- 3 files changed, 7 insertions(+), 26 deletions(-) diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index d768bc608a..d27d49ccb6 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -48,11 +48,10 @@ static void set_clock_sources(void) clock_configure_source(sdmmc3, PLLP, 48000); clock_configure_source(sdmmc4, PLLP, 48000); - /* PLLP and PLLM are switched for HOST1x for no apparent reason. */ + /* PLLP and PLLM are switched for HOST1x for no apparent reason. + * Hence, we do not use the constants. */ write32(4 /* PLLP! */ << CLK_SOURCE_SHIFT | - /* TODO(rminnich): The divisor isn't accurate enough to get to - * 144MHz (it goes to 163 instead). What should we do here? */ - CLK_DIVIDER(TEGRA_PLLP_KHZ, 144000), + CLK_DIVIDER(TEGRA_PLLP_KHZ, 408000), &clk_rst->clk_src_host1x); /* DISP1 doesn't support a divisor. Use PLLC which runs at 600MHz. */ @@ -202,7 +201,8 @@ static void mainboard_init(device_t dev) { set_clock_sources(); clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | - CLK_L_SDMMC4 | CLK_L_USBD, + CLK_L_SDMMC4 | CLK_L_USBD | + CLK_L_DISP1 | CLK_L_HOST1X, CLK_H_EMC | CLK_H_I2C2 | CLK_H_SBC1 | CLK_H_PMC | CLK_H_MEM | CLK_H_USB3, CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3, diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 17276b3b55..eb8bd7ac7c 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -213,8 +213,9 @@ void sor_clock_stop(void) void sor_clock_start(void) { - setbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0 | SOR0_CLK_SEL1); + setbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0); } + static void init_pll(u32 *base, u32 *misc, const union pll_fields pll) { u32 dividers = pll.div.n << PLL_BASE_DIVN_SHIFT | diff --git a/src/soc/nvidia/tegra124/displayhack.c b/src/soc/nvidia/tegra124/displayhack.c index 5777fe4fe8..88ff177143 100644 --- a/src/soc/nvidia/tegra124/displayhack.c +++ b/src/soc/nvidia/tegra124/displayhack.c @@ -50,30 +50,10 @@ int dpaux_read(u32 addr, u32 size, u8 * data); void init_dca_regs(void) { - struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE; // u32 val; printk(BIOS_SPEW, "JZ: %s: entry\n", __func__); -#define SWR_DISP1_RST (1 << 27) -#define SWR_HOST1X_RST (1 << 28) -#define CLK_ENB_DISP1 SWR_DISP1_RST -#define CLK_ENB_HOST1X SWR_HOST1X_RST -// REG(CLK_RST_CONTROLLER_RST_DEVICES_L_0, SWR_DISP1_RST, 1); -// REG(CLK_RST_CONTROLLER_RST_DEVICES_L_0, SWR_DISP1_RST, 0); -// REG(CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0, CLK_ENB_DISP1, 1); - /* enable disp1 */ - setbits_le32(&clkrst->rst_dev_l, SWR_DISP1_RST); // Set Reset - clrbits_le32(&clkrst->rst_dev_l, SWR_DISP1_RST); // Clear Reset - setbits_le32(&clkrst->clk_out_enb_l, CLK_ENB_DISP1); // Set Enable - WRITEL(0x00000000, (void *)(0x60006000 + 0x138)); // CLK_SOURCE_DISP1 = PLLP -// WRITEL(0x40000000, (void *)(0x60006000 + 0x138)); // CLK_SOURCE_DISP1 = PLLD - /* enable host1x */ - clrbits_le32(&clkrst->rst_dev_l, SWR_HOST1X_RST); // Clear Reset - setbits_le32(&clkrst->clk_out_enb_l, CLK_ENB_HOST1X); // Set Enable - WRITEL(0x80000000, (void *)(0x60006000 + 0x180)); // CLK_SOURCE_HOST1X = PLLP -// WRITEL(0x40000000, (0x60006000 + 0x180)); // CLK_SOURCE_HOST1X = PLLC - #if 1 #define DCA_WRITE(reg, val) \ { \