From 32c78b7e22fb63855f74a72cd250b31a14b373b4 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 20 Apr 2025 22:32:30 -0500 Subject: [PATCH] soc/intel/skylake: Hook up S0ix setting to option API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hook up the s0ix_enable setting to the option API, so it can be changed at runtime without recompilation. Default to the value set by the mainboard. Change-Id: I1684439755db9d8194ac5533513e65c9ba8f0768 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/87391 Tested-by: build bot (Jenkins) Reviewed-by: Jérémy Compostella --- src/soc/intel/skylake/chip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 715c008666..0356c3e8dd 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -417,6 +417,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; params->PchPmDeepSxPol = config->PmConfigDeepSxPol; + config->s0ix_enable = get_uint_option("s0ix_enable", config->s0ix_enable); params->PchPmSlpS0Enable = config->s0ix_enable; params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert; params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert;