From 31c91e811b9e07e7bcba6b9f8f5720a31322eb21 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 1 May 2014 09:01:14 -0700 Subject: [PATCH] broadwell: Create romstage header file Put all the exported romstage functions (that are not also defined in ramstage) into broadwell/romstage.h for easy access. Some of the stuff in this file is not used yet but will be part of a later commit. BUG=chrome-os-partner:28234 TEST=None Change-Id: I69db33ba95afa3c3868c7c09ed53ed80567d17f4 Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/198740 Reviewed-by: Aaron Durbin --- src/soc/intel/broadwell/broadwell/cpu.h | 33 ---------- src/soc/intel/broadwell/broadwell/me.h | 7 --- src/soc/intel/broadwell/broadwell/pch.h | 9 --- src/soc/intel/broadwell/broadwell/romstage.h | 63 +++++++++++++++++++ .../intel/broadwell/broadwell/systemagent.h | 2 - 5 files changed, 63 insertions(+), 51 deletions(-) create mode 100644 src/soc/intel/broadwell/broadwell/romstage.h diff --git a/src/soc/intel/broadwell/broadwell/cpu.h b/src/soc/intel/broadwell/broadwell/cpu.h index ae163fddd7..6ac09137aa 100644 --- a/src/soc/intel/broadwell/broadwell/cpu.h +++ b/src/soc/intel/broadwell/broadwell/cpu.h @@ -61,39 +61,6 @@ #if !defined(__ROMCC__) // FIXME romcc should handle below constructs -#if defined(__PRE_RAM__) -struct pei_data; -struct rcba_config_instruction; -struct romstage_params { - struct pei_data *pei_data; - const void *gpio_map; - const struct rcba_config_instruction *rcba_config; - unsigned long bist; - void (*copy_spd)(struct pei_data *); -}; -void mainboard_romstage_entry(unsigned long bist); -void romstage_common(const struct romstage_params *params); -/* romstage_main is called from the cache-as-ram assembly file. The return - * value is the stack value to be used for romstage once cache-as-ram is - * torn down. The following values are pushed onto the stack to setup the - * MTRRs: - * +0: Number of MTRRs - * +4: MTTR base 0 31:0 - * +8: MTTR base 0 63:32 - * +12: MTTR mask 0 31:0 - * +16: MTTR mask 0 63:32 - * +20: MTTR base 1 31:0 - * +24: MTTR base 1 63:32 - * +28: MTTR mask 1 31:0 - * +32: MTTR mask 1 63:32 - * ... - */ -void * asmlinkage romstage_main(unsigned long bist); -/* romstage_after_car() is the C function called after cache-as-ram has - * been torn down. It is responsible for loading the ramstage. */ -void romstage_after_car(void); -#endif - #ifdef __SMM__ /* Lock MSRs */ void intel_cpu_haswell_finalize_smm(void); diff --git a/src/soc/intel/broadwell/broadwell/me.h b/src/soc/intel/broadwell/broadwell/me.h index 91b19d603c..08a5d425f0 100644 --- a/src/soc/intel/broadwell/broadwell/me.h +++ b/src/soc/intel/broadwell/broadwell/me.h @@ -329,13 +329,6 @@ typedef enum { /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2); -#ifdef __PRE_RAM__ -void intel_early_me_status(void); -int intel_early_me_init(void); -int intel_early_me_uma_size(void); -int intel_early_me_init_done(u8 status); -#endif - #ifdef __SMM__ void intel_me_finalize_smm(void); void intel_me8_finalize_smm(void); diff --git a/src/soc/intel/broadwell/broadwell/pch.h b/src/soc/intel/broadwell/broadwell/pch.h index c38753e5b6..eab65e279b 100644 --- a/src/soc/intel/broadwell/broadwell/pch.h +++ b/src/soc/intel/broadwell/broadwell/pch.h @@ -59,15 +59,6 @@ void pch_log_state(void); #endif void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); - -#else -void enable_smbus(void); -void enable_usb_bar(void); -int early_spi_read(u32 offset, u32 size, u8 *buffer); -int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config); -void pch_enable_lpc(void); -#endif /* !__PRE_RAM__ && !__SMM__ */ #endif /* __ASSEMBLER__ */ diff --git a/src/soc/intel/broadwell/broadwell/romstage.h b/src/soc/intel/broadwell/broadwell/romstage.h new file mode 100644 index 0000000000..d48ec13106 --- /dev/null +++ b/src/soc/intel/broadwell/broadwell/romstage.h @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BROADWELL_ROMSTAGE_H_ +#define _BROADWELL_ROMSTAGE_H_ + +#include +#include + +#define NUM_ROMSTAGE_TS 4 +struct romstage_timestamps { + uint64_t times[NUM_ROMSTAGE_TS]; + int count; +}; + +struct romstage_params { + struct romstage_timestamps ts; + unsigned long bist; + struct pei_data *pei_data; +}; + +void mainboard_romstage_entry(struct romstage_params *params); +void romstage_common(struct romstage_params *params); +void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo, + uint32_t tsc_high); +void asmlinkage romstage_after_car(void); +void raminit(struct pei_data *pei_data); +void *setup_stack_and_mttrs(void); + +struct chipset_power_state; +struct chipset_power_state *fill_power_state(void); +void report_platform_info(void); +void report_memory_config(void); + +void set_max_freq(void); + +void systemagent_early_init(void); +void pch_early_init(void); +void intel_early_me_status(void); + +void enable_smbus(void); +int smbus_read_byte(unsigned device, unsigned address); + +int early_spi_read(u32 offset, u32 size, u8 *buffer); +int early_spi_read_wpsr(u8 *sr); + +#endif diff --git a/src/soc/intel/broadwell/broadwell/systemagent.h b/src/soc/intel/broadwell/broadwell/systemagent.h index a0f7a76773..a8dd4b8b05 100644 --- a/src/soc/intel/broadwell/broadwell/systemagent.h +++ b/src/soc/intel/broadwell/broadwell/systemagent.h @@ -187,7 +187,6 @@ static inline void barrier(void) { asm("" ::: "memory"); } #ifdef __SMM__ void intel_northbridge_haswell_finalize_smm(void); #else /* !__SMM__ */ -void haswell_early_initialization(int chipset_type); void haswell_late_initialization(void); void set_translation_table(int start, int end, u64 base, int inc); @@ -197,7 +196,6 @@ void dump_pci_device(unsigned dev); void dump_pci_devices(void); void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); -void report_platform_info(void); #endif /* !__SMM__ */