diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 0a23e08c10..45519611ab 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -464,17 +464,6 @@ void fast_spi_set_bde(void)
 	pci_or_config32(dev, SPI_BIOS_DECODE_EN, SPI_BIOS_DECODE_LOCK);
 }
 
-/* Set FAST_SPIBAR + SPIBAR_SFDP0_VSCC0 (0xc4) Vendor Control Lock */
-void fast_spi_set_vcl(void)
-{
-	void *spibar = fast_spi_get_bar();
-	uint32_t vcss;
-
-	vcss = read32(spibar + SPIBAR_SFDP0_VSCC0);
-	vcss |= SPIBAR_SFDP0_VSCC0_VCL;
-	write32(spibar + SPIBAR_SFDP0_VSCC0, vcss);
-}
-
 void fast_spi_clear_outstanding_status(void)
 {
 	void *spibar = fast_spi_get_bar();
diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
index 46b4f48693..716f16a07a 100644
--- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h
+++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
@@ -107,9 +107,5 @@ void fast_spi_cache_ext_bios_postcar(struct postcar_frame *pcf);
  * Set FAST_SPIBAR BIOS Decode Lock bit
  */
 void fast_spi_set_bde(void);
-/*
- * Set FAST_SPIBAR Vendor Component Lock bit.
- */
-void fast_spi_set_vcl(void);
 
 #endif	/* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */
diff --git a/src/soc/intel/xeon_sp/ebg/lockdown.c b/src/soc/intel/xeon_sp/ebg/lockdown.c
index 694e4a24a3..4ced721881 100644
--- a/src/soc/intel/xeon_sp/ebg/lockdown.c
+++ b/src/soc/intel/xeon_sp/ebg/lockdown.c
@@ -13,6 +13,5 @@ void spi_lockdown_config(int chipset_lockdown)
 {
 	if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
 		fast_spi_set_bde();
-		fast_spi_set_vcl();
 	}
 }
diff --git a/src/soc/intel/xeon_sp/ibl/lockdown.c b/src/soc/intel/xeon_sp/ibl/lockdown.c
index 694e4a24a3..4ced721881 100644
--- a/src/soc/intel/xeon_sp/ibl/lockdown.c
+++ b/src/soc/intel/xeon_sp/ibl/lockdown.c
@@ -13,6 +13,5 @@ void spi_lockdown_config(int chipset_lockdown)
 {
 	if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
 		fast_spi_set_bde();
-		fast_spi_set_vcl();
 	}
 }