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UPSTREAM: soc/intel/skylake: Configure C-state interrupt response time

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Program C3/C7/C10 interrupt response time for all cores.

BUG=none
BRANCH=none
TEST=none

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 481b364222
Original-Change-Id: I4f47502e1c212118d7cc89d4de60a1854072964a
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19675
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I844e26eca1c803364e528ee0d4d5895b268d0893
Reviewed-on: https://chromium-review.googlesource.com/506903
This commit is contained in:
Subrata Banik 2017-05-12 11:29:43 +05:30 • committed by chrome-bot
commit 3138a60d48
1 changed files with 41 additions and 0 deletions
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41
src/soc/intel/skylake/cpu.c
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@ -360,6 +360,44 @@ static void configure_mca(void)
}
}
static void configure_c_states(void)
{
msr_t msr;
/* C-state Interrupt Response Latency Control 0 - package C3 latency */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr);
/* C-state Interrupt Response Latency Control 1 - package C6/C7 short */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr);
/* C-state Interrupt Response Latency Control 2 - package C6/C7 long */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
/* C-state Interrupt Response Latency Control 3 - package C8 */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS |
C_STATE_LATENCY_CONTROL_3_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
/* C-state Interrupt Response Latency Control 4 - package C9 */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS |
C_STATE_LATENCY_CONTROL_4_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
/* C-state Interrupt Response Latency Control 5 - package C10 */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS |
C_STATE_LATENCY_CONTROL_5_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
}
/* All CPUs including BSP will run the following function. */
static void cpu_core_init(device_t cpu)
{
@ -370,6 +408,9 @@ static void cpu_core_init(device_t cpu)
enable_lapic_tpr();
setup_lapic();
/* Configure c-state interrupt response time */
configure_c_states();
/* Configure Enhanced SpeedStep and Thermal Sensors */
configure_misc();