From 311b0568c5de627435a5b035a7a1e40ecc2672f8 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Wed, 15 Jan 2014 17:15:44 +0800 Subject: [PATCH] tegra124: Revise sdram_param.h for Coreboot. The sdram_param.h from cbootimage has different type and #ifdef names that should be changed to comply with Coreboot. Note we also changed field names so it will be easier to cope with translating BCT config file (*.cfg) into simple C structure definition. BUG=none TEST=none Change-Id: I41fbc628da920863b4ae3d8795cb6dfe4fd31dca Reviewed-on: https://chromium-review.googlesource.com/182614 Reviewed-by: Julius Werner Commit-Queue: Hung-Te Lin Tested-by: Hung-Te Lin --- src/soc/nvidia/tegra124/sdram_param.h | 658 +++++++++++++------------- 1 file changed, 331 insertions(+), 327 deletions(-) diff --git a/src/soc/nvidia/tegra124/sdram_param.h b/src/soc/nvidia/tegra124/sdram_param.h index 34f537eb51..e108c2bafc 100644 --- a/src/soc/nvidia/tegra124/sdram_param.h +++ b/src/soc/nvidia/tegra124/sdram_param.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -20,479 +21,480 @@ /** * Defines the SDRAM parameter structure. * - * Note that PLLM is used by EMC. + * Note that PLLM is used by EMC. The field names are in camel case to ease + * directly converting BCT config files (*.cfg) into C structure. */ -#ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T124_H -#define INCLUDED_NVBOOT_SDRAM_PARAM_T124_H +#ifndef __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ +#define __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ -#define NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS 27 +#include +#include -typedef enum { +enum { /* Specifies the memory type to be undefined */ - nvboot_memory_type_none = 0, + MEMORY_TYPE_NONE = 0, /* Specifies the memory type to be DDR SDRAM */ - nvboot_memory_type_ddr = 0, + MEMORY_TYPE_DDR = 0, /* Specifies the memory type to be LPDDR SDRAM */ - nvboot_memory_type_lpddr = 0, + MEMORY_TYPE_LPDDR = 0, /* Specifies the memory type to be DDR2 SDRAM */ - nvboot_memory_type_ddr2 = 0, + MEMORY_TYPE_DDR2 = 0, /* Specifies the memory type to be LPDDR2 SDRAM */ - nvboot_memory_type_lpddr2, + MEMORY_TYPE_LPDDR2, /* Specifies the memory type to be DDR3 SDRAM */ - nvboot_memory_type_ddr3, + MEMORY_TYPE_DDR3, - nvboot_memory_type_num, - nvboot_memory_type_force32 = 0x7FFFFFF -} nvboot_memory_type; + MEMORY_TYPE_NUM, + MEMORY_TYPE_FORCE32 = 0X7FFFFFF +}; /** * Defines the SDRAM parameter structure */ -typedef struct nvboot_sdram_params_rec { - /* sdram data structure generated by tool warmboot_code_gen */ +struct sdram_params { /* Specifies the type of memory device */ - nvboot_memory_type memory_type; + uint32_t memory_type; /* MC/EMC clock source configuration */ /* Specifies the M value for PllM */ - u_int32_t pllm_input_divider; + uint32_t PllMInputDivider; /* Specifies the N value for PllM */ - u_int32_t pllm_feedback_divider; + uint32_t PllMFeedbackDivider; /* Specifies the time to wait for PLLM to lock (in microseconds) */ - u_int32_t pllm_stable_time; + uint32_t PllMStableTime; /* Specifies misc. control bits */ - u_int32_t pllm_setup_control; + uint32_t PllMSetupControl; /* Enables the Div by 2 */ - u_int32_t pllm_select_div2; + uint32_t PllMSelectDiv2; /* Powers down VCO output Level shifter */ - u_int32_t pllm_pdlshift_ph45; + uint32_t PllMPDLshiftPh45; /* Powers down VCO output Level shifter */ - u_int32_t pllm_pdlshift_ph90; + uint32_t PllMPDLshiftPh90; /* Powers down VCO output Level shifter */ - u_int32_t pllm_pdlshift_ph135; + uint32_t PllMPDLshiftPh135; /* Specifies value for Charge Pump Gain Control */ - u_int32_t pllm_kcp; + uint32_t PllMKCP; /* Specifies VCO gain */ - u_int32_t pllm_kvco; + uint32_t PllMKVCO; /* Spare BCT param */ - u_int32_t emc_bct_spare0; + uint32_t EmcBctSpare0; /* Spare BCT param */ - u_int32_t emc_bct_spare1; + uint32_t EmcBctSpare1; /* Spare BCT param */ - u_int32_t emc_bct_spare2; + uint32_t EmcBctSpare2; /* Spare BCT param */ - u_int32_t emc_bct_spare3; + uint32_t EmcBctSpare3; /* Spare BCT param */ - u_int32_t emc_bct_spare4; + uint32_t EmcBctSpare4; /* Spare BCT param */ - u_int32_t emc_bct_spare5; + uint32_t EmcBctSpare5; /* Spare BCT param */ - u_int32_t emc_bct_spare6; + uint32_t EmcBctSpare6; /* Spare BCT param */ - u_int32_t emc_bct_spare7; + uint32_t EmcBctSpare7; /* Spare BCT param */ - u_int32_t emc_bct_spare8; + uint32_t EmcBctSpare8; /* Spare BCT param */ - u_int32_t emc_bct_spare9; + uint32_t EmcBctSpare9; /* Spare BCT param */ - u_int32_t emc_bct_spare10; + uint32_t EmcBctSpare10; /* Spare BCT param */ - u_int32_t emc_bct_spare11; + uint32_t EmcBctSpare11; /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ - u_int32_t emc_clock_source; + uint32_t EmcClockSource; /* Auto-calibration of EMC pads */ /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ - u_int32_t emc_auto_cal_interval; + uint32_t EmcAutoCalInterval; /* * Specifies the value for EMC_AUTO_CAL_CONFIG * Note: Trigger bits are set by the SDRAM code. */ - u_int32_t emc_auto_cal_config; + uint32_t EmcAutoCalConfig; /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ - u_int32_t emc_auto_cal_config2; + uint32_t EmcAutoCalConfig2; /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ - u_int32_t emc_auto_cal_config3; + uint32_t EmcAutoCalConfig3; /* * Specifies the time for the calibration * to stabilize (in microseconds) */ - u_int32_t emc_auto_cal_wait; + uint32_t EmcAutoCalWait; /* * DRAM size information * Specifies the value for EMC_ADR_CFG */ - u_int32_t emc_adr_cfg; + uint32_t EmcAdrCfg; /* * Specifies the time to wait after asserting pin * CKE (in microseconds) */ - u_int32_t emc_pin_program_wait; + uint32_t EmcPinProgramWait; /* Specifies the extra delay before/after pin RESET/CKE command */ - u_int32_t emc_pin_extra_wait; + uint32_t EmcPinExtraWait; /* * Specifies the extra delay after the first writing * of EMC_TIMING_CONTROL */ - u_int32_t emc_timing_control_wait; + uint32_t EmcTimingControlWait; /* Timing parameters required for the SDRAM */ /* Specifies the value for EMC_RC */ - u_int32_t emc_rc; + uint32_t EmcRc; /* Specifies the value for EMC_RFC */ - u_int32_t emc_rfc; + uint32_t EmcRfc; /* Specifies the value for EMC_RFC_SLR */ - u_int32_t emc_rfc_slr; + uint32_t EmcRfcSlr; /* Specifies the value for EMC_RAS */ - u_int32_t emc_ras; + uint32_t EmcRas; /* Specifies the value for EMC_RP */ - u_int32_t emc_rp; + uint32_t EmcRp; /* Specifies the value for EMC_R2R */ - u_int32_t emc_r2r; + uint32_t EmcR2r; /* Specifies the value for EMC_W2W */ - u_int32_t emc_w2w; + uint32_t EmcW2w; /* Specifies the value for EMC_R2W */ - u_int32_t emc_r2w; + uint32_t EmcR2w; /* Specifies the value for EMC_W2R */ - u_int32_t emc_w2r; + uint32_t EmcW2r; /* Specifies the value for EMC_R2P */ - u_int32_t emc_r2p; + uint32_t EmcR2p; /* Specifies the value for EMC_W2P */ - u_int32_t emc_w2p; + uint32_t EmcW2p; /* Specifies the value for EMC_RD_RCD */ - u_int32_t emc_rd_rcd; + uint32_t EmcRdRcd; /* Specifies the value for EMC_WR_RCD */ - u_int32_t emc_wr_rcd; + uint32_t EmcWrRcd; /* Specifies the value for EMC_RRD */ - u_int32_t emc_rrd; + uint32_t EmcRrd; /* Specifies the value for EMC_REXT */ - u_int32_t emc_rext; + uint32_t EmcRext; /* Specifies the value for EMC_WEXT */ - u_int32_t emc_wext; + uint32_t EmcWext; /* Specifies the value for EMC_WDV */ - u_int32_t emc_wdv; + uint32_t EmcWdv; /* Specifies the value for EMC_WDV_MASK */ - u_int32_t emc_wdv_mask; + uint32_t EmcWdvMask; /* Specifies the value for EMC_QUSE */ - u_int32_t emc_quse; + uint32_t EmcQUse; /* Specifies the value for EMC_QUSE_WIDTH */ - u_int32_t emc_quse_width; + uint32_t EmcQuseWidth; /* Specifies the value for EMC_IBDLY */ - u_int32_t emc_ibdly; + uint32_t EmcIbdly; /* Specifies the value for EMC_EINPUT */ - u_int32_t emc_einput; + uint32_t EmcEInput; /* Specifies the value for EMC_EINPUT_DURATION */ - u_int32_t emc_einput_duration; + uint32_t EmcEInputDuration; /* Specifies the value for EMC_PUTERM_EXTRA */ - u_int32_t emc_puterm_extra; + uint32_t EmcPutermExtra; /* Specifies the value for EMC_PUTERM_WIDTH */ - u_int32_t emc_puterm_width; + uint32_t EmcPutermWidth; /* Specifies the value for EMC_PUTERM_ADJ */ - u_int32_t emc_puterm_adj; + uint32_t EmcPutermAdj; /* Specifies the value for EMC_CDB_CNTL_1 */ - u_int32_t emc_cdb_cntl1; + uint32_t EmcCdbCntl1; /* Specifies the value for EMC_CDB_CNTL_2 */ - u_int32_t emc_cdb_cntl2; + uint32_t EmcCdbCntl2; /* Specifies the value for EMC_CDB_CNTL_3 */ - u_int32_t emc_cdb_cntl3; + uint32_t EmcCdbCntl3; /* Specifies the value for EMC_QRST */ - u_int32_t emc_qrst; + uint32_t EmcQRst; /* Specifies the value for EMC_QSAFE */ - u_int32_t emc_qsafe; + uint32_t EmcQSafe; /* Specifies the value for EMC_RDV */ - u_int32_t emc_rdv; + uint32_t EmcRdv; /* Specifies the value for EMC_RDV_MASK */ - u_int32_t emc_rdv_mask; + uint32_t EmcRdvMask; /* Specifies the value for EMC_QPOP */ - u_int32_t emc_qpop; + uint32_t EmcQpop; /* Specifies the value for EMC_CTT */ - u_int32_t emc_ctt; + uint32_t EmcCtt; /* Specifies the value for EMC_CTT_DURATION */ - u_int32_t emc_ctt_duration; + uint32_t EmcCttDuration; /* Specifies the value for EMC_REFRESH */ - u_int32_t emc_refresh; + uint32_t EmcRefresh; /* Specifies the value for EMC_BURST_REFRESH_NUM */ - u_int32_t emc_burst_refresh_num; + uint32_t EmcBurstRefreshNum; /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ - u_int32_t emc_prerefresh_req_cnt; + uint32_t EmcPreRefreshReqCnt; /* Specifies the value for EMC_PDEX2WR */ - u_int32_t emc_pdex2wr; + uint32_t EmcPdEx2Wr; /* Specifies the value for EMC_PDEX2RD */ - u_int32_t emc_pdex2rd; + uint32_t EmcPdEx2Rd; /* Specifies the value for EMC_PCHG2PDEN */ - u_int32_t emc_pchg2pden; + uint32_t EmcPChg2Pden; /* Specifies the value for EMC_ACT2PDEN */ - u_int32_t emc_act2pden; + uint32_t EmcAct2Pden; /* Specifies the value for EMC_AR2PDEN */ - u_int32_t emc_ar2pden; + uint32_t EmcAr2Pden; /* Specifies the value for EMC_RW2PDEN */ - u_int32_t emc_rw2pden; + uint32_t EmcRw2Pden; /* Specifies the value for EMC_TXSR */ - u_int32_t emc_txsr; + uint32_t EmcTxsr; /* Specifies the value for EMC_TXSRDLL */ - u_int32_t emc_txsr_dll; + uint32_t EmcTxsrDll; /* Specifies the value for EMC_TCKE */ - u_int32_t emc_tcke; + uint32_t EmcTcke; /* Specifies the value for EMC_TCKESR */ - u_int32_t emc_tckesr; + uint32_t EmcTckesr; /* Specifies the value for EMC_TPD */ - u_int32_t emc_tpd; + uint32_t EmcTpd; /* Specifies the value for EMC_TFAW */ - u_int32_t emc_tfaw; + uint32_t EmcTfaw; /* Specifies the value for EMC_TRPAB */ - u_int32_t emc_trpab; + uint32_t EmcTrpab; /* Specifies the value for EMC_TCLKSTABLE */ - u_int32_t emc_tclkstable; + uint32_t EmcTClkStable; /* Specifies the value for EMC_TCLKSTOP */ - u_int32_t emc_tclkstop; + uint32_t EmcTClkStop; /* Specifies the value for EMC_TREFBW */ - u_int32_t emc_trefbw; + uint32_t EmcTRefBw; /* FBIO configuration values */ /* Specifies the value for EMC_FBIO_CFG5 */ - u_int32_t emc_fbio_cfg5; + uint32_t EmcFbioCfg5; /* Specifies the value for EMC_FBIO_CFG6 */ - u_int32_t emc_fbio_cfg6; + uint32_t EmcFbioCfg6; /* Specifies the value for EMC_FBIO_SPARE */ - u_int32_t emc_fbio_spare; + uint32_t EmcFbioSpare; /* Specifies the value for EMC_CFG_RSV */ - u_int32_t emc_cfg_rsv; + uint32_t EmcCfgRsv; /* MRS command values */ /* Specifies the value for EMC_MRS */ - u_int32_t emc_mrs; + uint32_t EmcMrs; /* Specifies the MP0 command to initialize mode registers */ - u_int32_t emc_emrs; + uint32_t EmcEmrs; /* Specifies the MP2 command to initialize mode registers */ - u_int32_t emc_emrs2; + uint32_t EmcEmrs2; /* Specifies the MP3 command to initialize mode registers */ - u_int32_t emc_emrs3; + uint32_t EmcEmrs3; /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ - u_int32_t emc_mrw1; + uint32_t EmcMrw1; /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ - u_int32_t emc_mrw2; + uint32_t EmcMrw2; /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ - u_int32_t emc_mrw3; + uint32_t EmcMrw3; /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ - u_int32_t emc_mrw4; + uint32_t EmcMrw4; /* * Specifies the programming to extra LPDDR2 Mode Register * at cold boot */ - u_int32_t emc_mrw_extra; + uint32_t EmcMrwExtra; /* * Specifies the programming to extra LPDDR2 Mode Register * at warm boot */ - u_int32_t emc_warm_boot_mrw_extra; + uint32_t EmcWarmBootMrwExtra; /* * Specify the enable of extra Mode Register programming at * warm boot */ - u_int32_t emc_warm_boot_extramode_reg_write_enable; + uint32_t EmcWarmBootExtraModeRegWriteEnable; /* * Specify the enable of extra Mode Register programming at * cold boot */ - u_int32_t emc_extramode_reg_write_enable; + uint32_t EmcExtraModeRegWriteEnable; /* Specifies the EMC_MRW reset command value */ - u_int32_t emc_mrw_reset_command; + uint32_t EmcMrwResetCommand; /* Specifies the EMC Reset wait time (in microseconds) */ - u_int32_t emc_mrw_reset_ninit_wait; + uint32_t EmcMrwResetNInitWait; /* Specifies the value for EMC_MRS_WAIT_CNT */ - u_int32_t emc_mrs_wait_cnt; + uint32_t EmcMrsWaitCnt; /* Specifies the value for EMC_MRS_WAIT_CNT2 */ - u_int32_t emc_mrs_wait_cnt2; + uint32_t EmcMrsWaitCnt2; /* EMC miscellaneous configurations */ /* Specifies the value for EMC_CFG */ - u_int32_t emc_cfg; + uint32_t EmcCfg; /* Specifies the value for EMC_CFG_2 */ - u_int32_t emc_cfg2; + uint32_t EmcCfg2; /* Specifies the pipe bypass controls */ - u_int32_t emc_cfg_pipe; + uint32_t EmcCfgPipe; /* Specifies the value for EMC_DBG */ - u_int32_t emc_dbg; + uint32_t EmcDbg; /* Specifies the value for EMC_CMDQ */ - u_int32_t emc_cmd_q; + uint32_t EmcCmdQ; /* Specifies the value for EMC_MC2EMCQ */ - u_int32_t emc_mc2emc_q; + uint32_t EmcMc2EmcQ; /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ - u_int32_t emc_dyn_self_ref_control; + uint32_t EmcDynSelfRefControl; /* Specifies the value for MEM_INIT_DONE */ - u_int32_t ahb_arbitration_xbar_ctrl_meminit_done; + uint32_t AhbArbitrationXbarCtrlMemInitDone; /* Specifies the value for EMC_CFG_DIG_DLL */ - u_int32_t emc_cfg_dig_dll; + uint32_t EmcCfgDigDll; /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ - u_int32_t emc_cfg_dig_dll_period; + uint32_t EmcCfgDigDllPeriod; /* Specifies the value of *DEV_SELECTN of various EMC registers */ - u_int32_t emc_dev_select; + uint32_t EmcDevSelect; /* Specifies the value for EMC_SEL_DPD_CTRL */ - u_int32_t emc_sel_dpd_ctrl; + uint32_t EmcSelDpdCtrl; /* Pads trimmer delays */ /* Specifies the value for EMC_DLL_XFORM_DQS0 */ - u_int32_t emc_dll_xform_dqs0; + uint32_t EmcDllXformDqs0; /* Specifies the value for EMC_DLL_XFORM_DQS1 */ - u_int32_t emc_dll_xform_dqs1; + uint32_t EmcDllXformDqs1; /* Specifies the value for EMC_DLL_XFORM_DQS2 */ - u_int32_t emc_dll_xform_dqs2; + uint32_t EmcDllXformDqs2; /* Specifies the value for EMC_DLL_XFORM_DQS3 */ - u_int32_t emc_dll_xform_dqs3; + uint32_t EmcDllXformDqs3; /* Specifies the value for EMC_DLL_XFORM_DQS4 */ - u_int32_t emc_dll_xform_dqs4; + uint32_t EmcDllXformDqs4; /* Specifies the value for EMC_DLL_XFORM_DQS5 */ - u_int32_t emc_dll_xform_dqs5; + uint32_t EmcDllXformDqs5; /* Specifies the value for EMC_DLL_XFORM_DQS6 */ - u_int32_t emc_dll_xform_dqs6; + uint32_t EmcDllXformDqs6; /* Specifies the value for EMC_DLL_XFORM_DQS7 */ - u_int32_t emc_dll_xform_dqs7; + uint32_t EmcDllXformDqs7; /* Specifies the value for EMC_DLL_XFORM_DQS8 */ - u_int32_t emc_dll_xform_dqs8; + uint32_t EmcDllXformDqs8; /* Specifies the value for EMC_DLL_XFORM_DQS9 */ - u_int32_t emc_dll_xform_dqs9; + uint32_t EmcDllXformDqs9; /* Specifies the value for EMC_DLL_XFORM_DQS10 */ - u_int32_t emc_dll_xform_dqs10; + uint32_t EmcDllXformDqs10; /* Specifies the value for EMC_DLL_XFORM_DQS11 */ - u_int32_t emc_dll_xform_dqs11; + uint32_t EmcDllXformDqs11; /* Specifies the value for EMC_DLL_XFORM_DQS12 */ - u_int32_t emc_dll_xform_dqs12; + uint32_t EmcDllXformDqs12; /* Specifies the value for EMC_DLL_XFORM_DQS13 */ - u_int32_t emc_dll_xform_dqs13; + uint32_t EmcDllXformDqs13; /* Specifies the value for EMC_DLL_XFORM_DQS14 */ - u_int32_t emc_dll_xform_dqs14; + uint32_t EmcDllXformDqs14; /* Specifies the value for EMC_DLL_XFORM_DQS15 */ - u_int32_t emc_dll_xform_dqs15; + uint32_t EmcDllXformDqs15; /* Specifies the value for EMC_DLL_XFORM_QUSE0 */ - u_int32_t emc_dll_xform_quse0; + uint32_t EmcDllXformQUse0; /* Specifies the value for EMC_DLL_XFORM_QUSE1 */ - u_int32_t emc_dll_xform_quse1; + uint32_t EmcDllXformQUse1; /* Specifies the value for EMC_DLL_XFORM_QUSE2 */ - u_int32_t emc_dll_xform_quse2; + uint32_t EmcDllXformQUse2; /* Specifies the value for EMC_DLL_XFORM_QUSE3 */ - u_int32_t emc_dll_xform_quse3; + uint32_t EmcDllXformQUse3; /* Specifies the value for EMC_DLL_XFORM_QUSE4 */ - u_int32_t emc_dll_xform_quse4; + uint32_t EmcDllXformQUse4; /* Specifies the value for EMC_DLL_XFORM_QUSE5 */ - u_int32_t emc_dll_xform_quse5; + uint32_t EmcDllXformQUse5; /* Specifies the value for EMC_DLL_XFORM_QUSE6 */ - u_int32_t emc_dll_xform_quse6; + uint32_t EmcDllXformQUse6; /* Specifies the value for EMC_DLL_XFORM_QUSE7 */ - u_int32_t emc_dll_xform_quse7; + uint32_t EmcDllXformQUse7; /* Specifies the value for EMC_DLL_XFORM_ADDR0 */ - u_int32_t emc_dll_xform_addr0; + uint32_t EmcDllXformAddr0; /* Specifies the value for EMC_DLL_XFORM_ADDR1 */ - u_int32_t emc_dll_xform_addr1; + uint32_t EmcDllXformAddr1; /* Specifies the value for EMC_DLL_XFORM_ADDR2 */ - u_int32_t emc_dll_xform_addr2; + uint32_t EmcDllXformAddr2; /* Specifies the value for EMC_DLL_XFORM_ADDR3 */ - u_int32_t emc_dll_xform_addr3; + uint32_t EmcDllXformAddr3; /* Specifies the value for EMC_DLL_XFORM_ADDR4 */ - u_int32_t emc_dll_xform_addr4; + uint32_t EmcDllXformAddr4; /* Specifies the value for EMC_DLL_XFORM_ADDR5 */ - u_int32_t emc_dll_xform_addr5; + uint32_t EmcDllXformAddr5; /* Specifies the value for EMC_DLL_XFORM_QUSE8 */ - u_int32_t emc_dll_xform_quse8; + uint32_t EmcDllXformQUse8; /* Specifies the value for EMC_DLL_XFORM_QUSE9 */ - u_int32_t emc_dll_xform_quse9; + uint32_t EmcDllXformQUse9; /* Specifies the value for EMC_DLL_XFORM_QUSE10 */ - u_int32_t emc_dll_xform_quse10; + uint32_t EmcDllXformQUse10; /* Specifies the value for EMC_DLL_XFORM_QUSE11 */ - u_int32_t emc_dll_xform_quse11; + uint32_t EmcDllXformQUse11; /* Specifies the value for EMC_DLL_XFORM_QUSE12 */ - u_int32_t emc_dll_xform_quse12; + uint32_t EmcDllXformQUse12; /* Specifies the value for EMC_DLL_XFORM_QUSE13 */ - u_int32_t emc_dll_xform_quse13; + uint32_t EmcDllXformQUse13; /* Specifies the value for EMC_DLL_XFORM_QUSE14 */ - u_int32_t emc_dll_xform_quse14; + uint32_t EmcDllXformQUse14; /* Specifies the value for EMC_DLL_XFORM_QUSE15 */ - u_int32_t emc_dll_xform_quse15; + uint32_t EmcDllXformQUse15; /* Specifies the value for EMC_DLI_TRIM_TXDQS0 */ - u_int32_t emc_dli_trim_tx_dqs0; + uint32_t EmcDliTrimTxDqs0; /* Specifies the value for EMC_DLI_TRIM_TXDQS1 */ - u_int32_t emc_dli_trim_tx_dqs1; + uint32_t EmcDliTrimTxDqs1; /* Specifies the value for EMC_DLI_TRIM_TXDQS2 */ - u_int32_t emc_dli_trim_tx_dqs2; + uint32_t EmcDliTrimTxDqs2; /* Specifies the value for EMC_DLI_TRIM_TXDQS3 */ - u_int32_t emc_dli_trim_tx_dqs3; + uint32_t EmcDliTrimTxDqs3; /* Specifies the value for EMC_DLI_TRIM_TXDQS4 */ - u_int32_t emc_dli_trim_tx_dqs4; + uint32_t EmcDliTrimTxDqs4; /* Specifies the value for EMC_DLI_TRIM_TXDQS5 */ - u_int32_t emc_dli_trim_tx_dqs5; + uint32_t EmcDliTrimTxDqs5; /* Specifies the value for EMC_DLI_TRIM_TXDQS6 */ - u_int32_t emc_dli_trim_tx_dqs6; + uint32_t EmcDliTrimTxDqs6; /* Specifies the value for EMC_DLI_TRIM_TXDQS7 */ - u_int32_t emc_dli_trim_tx_dqs7; + uint32_t EmcDliTrimTxDqs7; /* Specifies the value for EMC_DLI_TRIM_TXDQS8 */ - u_int32_t emc_dli_trim_tx_dqs8; + uint32_t EmcDliTrimTxDqs8; /* Specifies the value for EMC_DLI_TRIM_TXDQS9 */ - u_int32_t emc_dli_trim_tx_dqs9; + uint32_t EmcDliTrimTxDqs9; /* Specifies the value for EMC_DLI_TRIM_TXDQS10 */ - u_int32_t emc_dli_trim_tx_dqs10; + uint32_t EmcDliTrimTxDqs10; /* Specifies the value for EMC_DLI_TRIM_TXDQS11 */ - u_int32_t emc_dli_trim_tx_dqs11; + uint32_t EmcDliTrimTxDqs11; /* Specifies the value for EMC_DLI_TRIM_TXDQS12 */ - u_int32_t emc_dli_trim_tx_dqs12; + uint32_t EmcDliTrimTxDqs12; /* Specifies the value for EMC_DLI_TRIM_TXDQS13 */ - u_int32_t emc_dli_trim_tx_dqs13; + uint32_t EmcDliTrimTxDqs13; /* Specifies the value for EMC_DLI_TRIM_TXDQS14 */ - u_int32_t emc_dli_trim_tx_dqs14; + uint32_t EmcDliTrimTxDqs14; /* Specifies the value for EMC_DLI_TRIM_TXDQS15 */ - u_int32_t emc_dli_trim_tx_dqs15; + uint32_t EmcDliTrimTxDqs15; /* Specifies the value for EMC_DLL_XFORM_DQ0 */ - u_int32_t emc_dll_xform_dq0; + uint32_t EmcDllXformDq0; /* Specifies the value for EMC_DLL_XFORM_DQ1 */ - u_int32_t emc_dll_xform_dq1; + uint32_t EmcDllXformDq1; /* Specifies the value for EMC_DLL_XFORM_DQ2 */ - u_int32_t emc_dll_xform_dq2; + uint32_t EmcDllXformDq2; /* Specifies the value for EMC_DLL_XFORM_DQ3 */ - u_int32_t emc_dll_xform_dq3; + uint32_t EmcDllXformDq3; /* Specifies the value for EMC_DLL_XFORM_DQ4 */ - u_int32_t emc_dll_xform_dq4; + uint32_t EmcDllXformDq4; /* Specifies the value for EMC_DLL_XFORM_DQ5 */ - u_int32_t emc_dll_xform_dq5; + uint32_t EmcDllXformDq5; /* Specifies the value for EMC_DLL_XFORM_DQ6 */ - u_int32_t emc_dll_xform_dq6; + uint32_t EmcDllXformDq6; /* Specifies the value for EMC_DLL_XFORM_DQ7 */ - u_int32_t emc_dll_xform_dq7; + uint32_t EmcDllXformDq7; /* * Specifies the delay after asserting CKE pin during a WarmBoot0 * sequence (in microseconds) */ - u_int32_t warm_boot_wait; + uint32_t WarmBootWait; /* Specifies the value for EMC_CTT_TERM_CTRL */ - u_int32_t emc_ctt_term_ctrl; + uint32_t EmcCttTermCtrl; /* Specifies the value for EMC_ODT_WRITE */ - u_int32_t emc_odt_write; + uint32_t EmcOdtWrite; /* Specifies the value for EMC_ODT_WRITE */ - u_int32_t emc_odt_read; + uint32_t EmcOdtRead; /* Periodic ZQ calibration */ @@ -500,304 +502,306 @@ typedef struct nvboot_sdram_params_rec { * Specifies the value for EMC_ZCAL_INTERVAL * Value 0 disables ZQ calibration */ - u_int32_t emc_zcal_interval; + uint32_t EmcZcalInterval; /* Specifies the value for EMC_ZCAL_WAIT_CNT */ - u_int32_t emc_zcal_wait_cnt; + uint32_t EmcZcalWaitCnt; /* Specifies the value for EMC_ZCAL_MRW_CMD */ - u_int32_t emc_zcal_mrw_cmd; + uint32_t EmcZcalMrwCmd; /* DRAM initialization sequence flow control */ /* Specifies the MRS command value for resetting DLL */ - u_int32_t emc_mrs_reset_dll; + uint32_t EmcMrsResetDll; /* Specifies the command for ZQ initialization of device 0 */ - u_int32_t emc_zcal_init_dev0; + uint32_t EmcZcalInitDev0; /* Specifies the command for ZQ initialization of device 1 */ - u_int32_t emc_zcal_init_dev1; + uint32_t EmcZcalInitDev1; /* * Specifies the wait time after programming a ZQ initialization * command (in microseconds) */ - u_int32_t emc_zcal_init_wait; + uint32_t EmcZcalInitWait; /* * Specifies the enable for ZQ calibration at cold boot [bit 0] * and warm boot [bit 1] */ - u_int32_t emc_zcal_warm_cold_boot_enables; + uint32_t EmcZcalWarmColdBootEnables; /* * Specifies the MRW command to LPDDR2 for ZQ calibration * on warmboot */ /* Is issued to both devices separately */ - u_int32_t emc_mrw_lpddr2zcal_warm_boot; + uint32_t EmcMrwLpddr2ZcalWarmBoot; /* * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot * Is issued to both devices separately */ - u_int32_t emc_zqcal_ddr3_warm_boot; + uint32_t EmcZqCalDdr3WarmBoot; /* * Specifies the wait time for ZQ calibration on warmboot * (in microseconds) */ - u_int32_t emc_zcal_warm_boot_wait; + uint32_t EmcZcalWarmBootWait; /* * Specifies the enable for DRAM Mode Register programming * at warm boot */ - u_int32_t emc_mrs_warm_boot_enable; + uint32_t EmcMrsWarmBootEnable; /* * Specifies the wait time after sending an MRS DLL reset command * in microseconds) */ - u_int32_t emc_mrs_reset_dll_wait; + uint32_t EmcMrsResetDllWait; /* Specifies the extra MRS command to initialize mode registers */ - u_int32_t emc_mrs_extra; + uint32_t EmcMrsExtra; /* Specifies the extra MRS command at warm boot */ - u_int32_t emc_warm_boot_mrs_extra; + uint32_t EmcWarmBootMrsExtra; /* Specifies the EMRS command to enable the DDR2 DLL */ - u_int32_t emc_emrs_ddr2_dll_enable; + uint32_t EmcEmrsDdr2DllEnable; /* Specifies the MRS command to reset the DDR2 DLL */ - u_int32_t emc_mrs_ddr2_dll_reset; + uint32_t EmcMrsDdr2DllReset; /* Specifies the EMRS command to set OCD calibration */ - u_int32_t emc_emrs_ddr2_ocd_calib; + uint32_t EmcEmrsDdr2OcdCalib; /* * Specifies the wait between initializing DDR and setting OCD * calibration (in microseconds) */ - u_int32_t emc_ddr2_wait; + uint32_t EmcDdr2Wait; /* Specifies the value for EMC_CLKEN_OVERRIDE */ - u_int32_t emc_clken_override; + uint32_t EmcClkenOverride; /* Specifies the value for MC_DIS_EXTRA_SNAP_LEVELS */ - u_int32_t mc_dis_extra_snap_levels; + uint32_t McDisExtraSnapLevels; /* * Specifies LOG2 of the extra refresh numbers after booting * Program 0 to disable */ - u_int32_t emc_extra_refresh_num; + uint32_t EmcExtraRefreshNum; /* Specifies the master override for all EMC clocks */ - u_int32_t emc_clken_override_allwarm_boot; + uint32_t EmcClkenOverrideAllWarmBoot; /* Specifies the master override for all MC clocks */ - u_int32_t mc_clken_override_allwarm_boot; + uint32_t McClkenOverrideAllWarmBoot; /* Specifies digital dll period, choosing between 4 to 64 ms */ - u_int32_t emc_cfg_dig_dll_period_warm_boot; + uint32_t EmcCfgDigDllPeriodWarmBoot; /* Pad controls */ /* Specifies the value for PMC_VDDP_SEL */ - u_int32_t pmc_vddp_sel; + uint32_t PmcVddpSel; /* Specifies the wait time after programming PMC_VDDP_SEL */ - u_int32_t pmc_vddp_sel_wait; + uint32_t PmcVddpSelWait; /* Specifies the value for PMC_DDR_PWR */ - u_int32_t pmc_ddr_pwr; + uint32_t PmcDdrPwr; /* Specifies the value for PMC_DDR_CFG */ - u_int32_t pmc_ddr_cfg; + uint32_t PmcDdrCfg; /* Specifies the value for PMC_IO_DPD3_REQ */ - u_int32_t pmc_io_dpd3_req; + uint32_t PmcIoDpd3Req; /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ - u_int32_t pmc_io_dpd3_req_wait; + uint32_t PmcIoDpd3ReqWait; /* Specifies the value for PMC_REG_SHORT */ - u_int32_t pmc_reg_short; + uint32_t PmcRegShort; /* Specifies the value for PMC_NO_IOPOWER */ - u_int32_t pmc_no_io_power; + uint32_t PmcNoIoPower; /* Specifies the wait time after programming PMC_POR_DPD_CTRL */ - u_int32_t pmc_por_dpd_ctrl_wait; + uint32_t PmcPorDpdCtrlWait; /* Specifies the value for EMC_XM2CMDPADCTRL */ - u_int32_t emc_xm2cmd_pad_ctrl; + uint32_t EmcXm2CmdPadCtrl; /* Specifies the value for EMC_XM2CMDPADCTRL2 */ - u_int32_t emc_xm2cmd_pad_ctrl2; + uint32_t EmcXm2CmdPadCtrl2; /* Specifies the value for EMC_XM2CMDPADCTRL3 */ - u_int32_t emc_xm2cmd_pad_ctrl3; + uint32_t EmcXm2CmdPadCtrl3; /* Specifies the value for EMC_XM2CMDPADCTRL4 */ - u_int32_t emc_xm2cmd_pad_ctrl4; + uint32_t EmcXm2CmdPadCtrl4; /* Specifies the value for EMC_XM2CMDPADCTRL5 */ - u_int32_t emc_xm2cmd_pad_ctrl5; + uint32_t EmcXm2CmdPadCtrl5; /* Specifies the value for EMC_XM2DQSPADCTRL */ - u_int32_t emc_xm2dqs_pad_ctrl; + uint32_t EmcXm2DqsPadCtrl; /* Specifies the value for EMC_XM2DQSPADCTRL2 */ - u_int32_t emc_xm2dqs_pad_ctrl2; + uint32_t EmcXm2DqsPadCtrl2; /* Specifies the value for EMC_XM2DQSPADCTRL3 */ - u_int32_t emc_xm2dqs_pad_ctrl3; + uint32_t EmcXm2DqsPadCtrl3; /* Specifies the value for EMC_XM2DQSPADCTRL4 */ - u_int32_t emc_xm2dqs_pad_ctrl4; + uint32_t EmcXm2DqsPadCtrl4; /* Specifies the value for EMC_XM2DQSPADCTRL5 */ - u_int32_t emc_xm2dqs_pad_ctrl5; + uint32_t EmcXm2DqsPadCtrl5; /* Specifies the value for EMC_XM2DQSPADCTRL6 */ - u_int32_t emc_xm2dqs_pad_ctrl6; + uint32_t EmcXm2DqsPadCtrl6; /* Specifies the value for EMC_XM2DQPADCTRL */ - u_int32_t emc_xm2dq_pad_ctrl; + uint32_t EmcXm2DqPadCtrl; /* Specifies the value for EMC_XM2DQPADCTRL2 */ - u_int32_t emc_xm2dq_pad_ctrl2; + uint32_t EmcXm2DqPadCtrl2; /* Specifies the value for EMC_XM2DQPADCTRL3 */ - u_int32_t emc_xm2dq_pad_ctrl3; + uint32_t EmcXm2DqPadCtrl3; /* Specifies the value for EMC_XM2CLKPADCTRL */ - u_int32_t emc_xm2clk_pad_ctrl; + uint32_t EmcXm2ClkPadCtrl; /* Specifies the value for EMC_XM2CLKPADCTRL2 */ - u_int32_t emc_xm2clk_pad_ctrl2; + uint32_t EmcXm2ClkPadCtrl2; /* Specifies the value for EMC_XM2COMPPADCTRL */ - u_int32_t emc_xm2comp_pad_ctrl; + uint32_t EmcXm2CompPadCtrl; /* Specifies the value for EMC_XM2VTTGENPADCTRL */ - u_int32_t emc_xm2vttgen_pad_ctrl; + uint32_t EmcXm2VttGenPadCtrl; /* Specifies the value for EMC_XM2VTTGENPADCTRL2 */ - u_int32_t emc_xm2vttgen_pad_ctrl2; + uint32_t EmcXm2VttGenPadCtrl2; /* Specifies the value for EMC_XM2VTTGENPADCTRL3 */ - u_int32_t emc_xm2vttgen_pad_ctrl3; + uint32_t EmcXm2VttGenPadCtrl3; /* Specifies the value for EMC_ACPD_CONTROL */ - u_int32_t emc_acpd_control; + uint32_t EmcAcpdControl; /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ - u_int32_t emc_swizzle_rank0_byte_cfg; + uint32_t EmcSwizzleRank0ByteCfg; /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ - u_int32_t emc_swizzle_rank0_byte0; + uint32_t EmcSwizzleRank0Byte0; /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ - u_int32_t emc_swizzle_rank0_byte1; + uint32_t EmcSwizzleRank0Byte1; /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ - u_int32_t emc_swizzle_rank0_byte2; + uint32_t EmcSwizzleRank0Byte2; /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ - u_int32_t emc_swizzle_rank0_byte3; + uint32_t EmcSwizzleRank0Byte3; /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ - u_int32_t emc_swizzle_rank1_byte_cfg; + uint32_t EmcSwizzleRank1ByteCfg; /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ - u_int32_t emc_swizzle_rank1_byte0; + uint32_t EmcSwizzleRank1Byte0; /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ - u_int32_t emc_swizzle_rank1_byte1; + uint32_t EmcSwizzleRank1Byte1; /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ - u_int32_t emc_swizzle_rank1_byte2; + uint32_t EmcSwizzleRank1Byte2; /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ - u_int32_t emc_swizzle_rank1_byte3; + uint32_t EmcSwizzleRank1Byte3; /* Specifies the value for EMC_DSR_VTTGEN_DRV */ - u_int32_t emc_dsr_vttgen_drv; + uint32_t EmcDsrVttgenDrv; /* Specifies the value for EMC_TXDSRVTTGEN */ - u_int32_t emc_txdsrvttgen; + uint32_t EmcTxdsrvttgen; /* Specifies the value for EMC_BGBIAS_CTL */ - u_int32_t emc_bgbias_ctl0; + uint32_t EmcBgbiasCtl0; /* DRAM size information */ /* Specifies the value for MC_EMEM_ADR_CFG */ - u_int32_t mc_emem_adr_cfg; + uint32_t McEmemAdrCfg; /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ - u_int32_t mc_emem_adr_cfg_dev0; + uint32_t McEmemAdrCfgDev0; /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ - u_int32_t mc_emem_adr_cfg_dev1; + uint32_t McEmemAdrCfgDev1; /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ - u_int32_t mc_emem_adr_cfg_bank_mask0; + uint32_t McEmemAdrCfgBankMask0; /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ - u_int32_t mc_emem_adr_cfg_bank_mask1; + uint32_t McEmemAdrCfgBankMask1; /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ - u_int32_t mc_emem_adr_cfg_bank_mask2; + uint32_t McEmemAdrCfgBankMask2; /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG3 */ - u_int32_t mc_emem_adr_cfg_bank_swizzle3; + uint32_t McEmemAdrCfgBankSwizzle3; /* * Specifies the value for MC_EMEM_CFG which holds the external memory * size (in KBytes) */ - u_int32_t mc_emem_cfg; + uint32_t McEmemCfg; /* MC arbitration configuration */ /* Specifies the value for MC_EMEM_ARB_CFG */ - u_int32_t mc_emem_arb_cfg; + uint32_t McEmemArbCfg; /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ - u_int32_t mc_emem_arb_outstanding_req; + uint32_t McEmemArbOutstandingReq; /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ - u_int32_t mc_emem_arb_timing_rcd; + uint32_t McEmemArbTimingRcd; /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ - u_int32_t mc_emem_arb_timing_rp; + uint32_t McEmemArbTimingRp; /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ - u_int32_t mc_emem_arb_timing_rc; + uint32_t McEmemArbTimingRc; /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ - u_int32_t mc_emem_arb_timing_ras; + uint32_t McEmemArbTimingRas; /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ - u_int32_t mc_emem_arb_timing_faw; + uint32_t McEmemArbTimingFaw; /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ - u_int32_t mc_emem_arb_timing_rrd; + uint32_t McEmemArbTimingRrd; /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ - u_int32_t mc_emem_arb_timing_rap2pre; + uint32_t McEmemArbTimingRap2Pre; /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ - u_int32_t mc_emem_arb_timing_wap2pre; + uint32_t McEmemArbTimingWap2Pre; /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ - u_int32_t mc_emem_arb_timing_r2r; + uint32_t McEmemArbTimingR2R; /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ - u_int32_t mc_emem_arb_timing_w2w; + uint32_t McEmemArbTimingW2W; /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ - u_int32_t mc_emem_arb_timing_r2w; + uint32_t McEmemArbTimingR2W; /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ - u_int32_t mc_emem_arb_timing_w2r; + uint32_t McEmemArbTimingW2R; /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ - u_int32_t mc_emem_arb_da_turns; + uint32_t McEmemArbDaTurns; /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ - u_int32_t mc_emem_arb_da_covers; + uint32_t McEmemArbDaCovers; /* Specifies the value for MC_EMEM_ARB_MISC0 */ - u_int32_t mc_emem_arb_misc0; + uint32_t McEmemArbMisc0; /* Specifies the value for MC_EMEM_ARB_MISC1 */ - u_int32_t mc_emem_arb_misc1; + uint32_t McEmemArbMisc1; /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ - u_int32_t mc_emem_arb_ring1_throttle; + uint32_t McEmemArbRing1Throttle; /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ - u_int32_t mc_emem_arb_override; + uint32_t McEmemArbOverride; /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ - u_int32_t mc_emem_arb_override1; + uint32_t McEmemArbOverride1; /* Specifies the value for MC_EMEM_ARB_RSV */ - u_int32_t mc_emem_arb_rsv; + uint32_t McEmemArbRsv; /* Specifies the value for MC_CLKEN_OVERRIDE */ - u_int32_t mc_clken_override; + uint32_t McClkenOverride; /* Specifies the value for MC_STAT_CONTROL */ - u_int32_t mc_stat_control; + uint32_t McStatControl; /* Specifies the value for MC_DISPLAY_SNAP_RING */ - u_int32_t mc_display_snap_ring; + uint32_t McDisplaySnapRing; /* Specifies the value for MC_VIDEO_PROTECT_BOM */ - u_int32_t mc_video_protect_bom; + uint32_t McVideoProtectBom; /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ - u_int32_t mc_video_protect_bom_adr_hi; + uint32_t McVideoProtectBomAdrHi; /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ - u_int32_t mc_video_protect_size_mb; + uint32_t McVideoProtectSizeMb; /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ - u_int32_t mc_video_protect_vpr_override; + uint32_t McVideoProtectVprOverride; /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ - u_int32_t mc_video_protect_vpr_override1; + uint32_t McVideoProtectVprOverride1; /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ - u_int32_t mc_video_protect_gpu_override0; + uint32_t McVideoProtectGpuOverride0; /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ - u_int32_t mc_video_protect_gpu_override1; + uint32_t McVideoProtectGpuOverride1; /* Specifies the value for MC_SEC_CARVEOUT_BOM */ - u_int32_t mc_sec_carveout_bom; + uint32_t McSecCarveoutBom; /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ - u_int32_t mc_sec_carveout_adr_hi; + uint32_t McSecCarveoutAdrHi; /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ - u_int32_t mc_sec_carveout_size_mb; + uint32_t McSecCarveoutSizeMb; /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ - u_int32_t mc_video_protect_write_access; + uint32_t McVideoProtectWriteAccess; /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ - u_int32_t mc_sec_carveout_protect_write_access; + uint32_t McSecCarveoutProtectWriteAccess; /* Specifies enable for CA training */ - u_int32_t emc_ca_training_enable; + uint32_t EmcCaTrainingEnable; /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL1 */ - u_int32_t emc_ca_training_timing_cntl1; + uint32_t EmcCaTrainingTimingCntl1; /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL2 */ - u_int32_t emc_ca_training_timing_cntl2; + uint32_t EmcCaTrainingTimingCntl2; /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ - u_int32_t swizzle_rank_byte_encode; + uint32_t SwizzleRankByteEncode; /* Specifies enable and offset for patched boot rom write */ - u_int32_t boot_rom_patch_control; + uint32_t BootRomPatchControl; /* Specifies data for patched boot rom write */ - u_int32_t boot_rom_patch_data; + uint32_t BootRomPatchData; /* Specifies the value for MC_MTS_CARVEOUT_BOM */ - u_int32_t mc_mts_carveout_bom; + uint32_t McMtsCarveoutBom; /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ - u_int32_t mc_mts_carveout_adr_hi; + uint32_t McMtsCarveoutAdrHi; /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ - u_int32_t mc_mts_carveout_size_mb; + uint32_t McMtsCarveoutSizeMb; /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ - u_int32_t mc_mts_carveout_reg_ctrl; + uint32_t McMtsCarveoutRegCtrl; /* End of generated code by warmboot_code_gen */ -} nvboot_sdram_params; -#endif /* #ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T124_H */ +}; +check_member(sdram_params, McMtsCarveoutRegCtrl, 0x4d0); + +#endif /* __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ */