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UPSTREAM: arch/arm/include/armv7/arch: Correct keyword organization in cpu.h

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Move the inline keyword in between the static keyword and the return
type.

BUG=none
BRANCH=none
TEST=none

Change-Id: I0cc7d5d5c123202231946193d65e9541d2ee630f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cfbb815efd
Original-Change-Id: Ibacc5ee9fabff7fec2abd5534312cf3ab1bb28cf
Original-Signed-off-by: Logan Carlson <logancarlson@google.com>
Original-Reviewed-on: https://review.coreboot.org/19991
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/523970
This commit is contained in:
Logan Carlson 2017-05-30 15:59:02 -06:00 • committed by chrome-bot
commit 30656586f4
1 changed files with 8 additions and 8 deletions
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16
src/arch/arm/include/armv7/arch/cpu.h
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@ -49,7 +49,7 @@ struct cpuinfo_arm {
/* Primitives for CPU and MP cores. */
/* read Main Id register (MIDR) */
inline static uint32_t read_midr(void)
static inline uint32_t read_midr(void)
{
uint32_t value;
asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r"(value));
@ -57,7 +57,7 @@ inline static uint32_t read_midr(void)
}
/* read Multiprocessor Affinity Register (MPIDR) */
inline static uint32_t read_mpidr(void)
static inline uint32_t read_mpidr(void)
{
uint32_t value;
asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r"(value));
@ -65,7 +65,7 @@ inline static uint32_t read_mpidr(void)
}
/* read Auxiliary Control Register (ACTLR) */
inline static uint32_t read_actlr(void)
static inline uint32_t read_actlr(void)
{
uint32_t val = 0;
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r"(val));
@ -73,31 +73,31 @@ inline static uint32_t read_actlr(void)
}
/* write Auxiliary Control Register (ACTLR) */
inline static void write_actlr(uint32_t val)
static inline void write_actlr(uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (val));
}
/* wait for interrupt. */
inline static void wfi(void)
static inline void wfi(void)
{
asm volatile ("wfi" : : : "memory");
}
/* wait for event. */
inline static void wfe(void)
static inline void wfe(void)
{
asm volatile ("wfe");
}
/* set event (to bring up cores in WFE state). */
inline static void sev(void)
static inline void sev(void)
{
asm volatile ("sev");
}
/* puts CPU into System mode and disable interrupts. */
inline static void set_system_mode(void)
static inline void set_system_mode(void)
{
asm volatile("msr cpsr_c, %0" :: "r"(0x1f | 0xc0));
}