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UPSTREAM: amd/mct/ddr3: Avoid using uninitialized register address in ECC setup

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Logic inside mct_EnableDimmEccEn_D uses an unintialized variable as
a register address under certain conditions.  Refactor mct_EnableDimmEccEn_D
to use the explicit address of the register in all cases.

BUG=none
BRANCH=none
TEST=none

Change-Id: If0a31097c60af1fa050b6794ed5d631a7aa4c0d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 590a3e1f6c
Original-Found-by: Coverity Scan #1347337
Original-Change-Id: I6bc50d0524ea255aa97c7071ec4813f6a3e9c2b8
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18079
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/428249
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Timothy Pearson 2017-01-09 17:54:35 -06:00 • committed by chrome-bot
commit 303afe6a03
1 changed files with 4 additions and 7 deletions
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11
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
View file

@ -2242,23 +2242,20 @@ void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 _DisableDramECC)
{
u32 val;
u32 reg;
u32 dev;
/* Enable ECC correction if it was previously disabled */
dev = pDCTstat->dev_dct;
if ((_DisableDramECC & 0x01) == 0x01) {
reg = 0x90;
val = Get_NB32_DCT(dev, 0, reg);
val = Get_NB32_DCT(dev, 0, 0x90);
val |= (1<<DimmEcEn);
Set_NB32_DCT(dev, 0, reg, val);
Set_NB32_DCT(dev, 0, 0x90, val);
}
if ((_DisableDramECC & 0x02) == 0x02) {
val = Get_NB32_DCT(dev, 1, reg);
val = Get_NB32_DCT(dev, 1, 0x90);
val |= (1<<DimmEcEn);
Set_NB32_DCT(dev, 1, reg, val);
Set_NB32_DCT(dev, 1, 0x90, val);
}
}