diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 8de99d2f95..a8f86a8e56 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <bootmode.h>
 #include <cpu/intel/common/common.h>
 #include <cpu/x86/msr.h>
 #include <elog.h>
@@ -13,7 +12,8 @@
 #include <soc/pcie.h>
 #include <soc/romstage.h>
 #include <static.h>
-#include <ux_locales.h>
+
+#include "ux.h"
 
 #define FSP_CLK_NOTUSED		0xff
 #define FSP_CLK_LAN		0x70
@@ -360,31 +360,16 @@ static void fill_fsp_event_handler(FSPM_UPD *mupd)
 
 static void fill_fspm_sign_of_life(FSPM_UPD *mupd)
 {
-	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 	FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd;
-	void *vbt;
-	size_t vbt_size;
 
 	if (arch_upd->NvsBufferPtr)
 		return;
 
 	/* To enhance the user experience, let's display on-screen guidance during memory
 	   training, acknowledging that the process may require patience. */
-
-	vbt = cbfs_map("vbt.bin", &vbt_size);
-	if (!vbt) {
-		printk(BIOS_ERR, "Could not load vbt.bin\n");
-		return;
-	}
-
 	printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n");
 	elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC);
-
-	m_cfg->VgaInitControl = 1;
-	m_cfg->VbtPtr = (efi_uintn_t)vbt;
-	m_cfg->VbtSize = vbt_size;
-	m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
-	m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
+	ux_inform_user_of_update_operation("memory training", mupd);
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)