From 2f1e67bbc79ed0c107b0cd68d84ea3924d1a4266 Mon Sep 17 00:00:00 2001 From: Daniel Peng Date: Thu, 28 Nov 2024 17:52:43 +0800 Subject: [PATCH] mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After modified the settings, it could be met the time sequence for this ILIT2901 touchscreen specification via our EE's measurements. 1. ILIT2901 Specification: ILI2901A-A202 Data Sheet_V1.2_20240128.pdf. 2. Double delay RST time to 12ms. 3. F/W calibration delay time is about 700ms after RST high. The tuned firmware version is 005c_0700.0000.0000.0006.bin. BUG=b:375986645 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot chromeos-bootimage 2. Verified the sequence correctly by EE. Change-Id: I15e30ee72541b4f12b3ec4ea509cb09dc29659ca Signed-off-by: Daniel Peng Reviewed-on: https://review.coreboot.org/c/coreboot/+/85363 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Daniel Peng --- .../google/brya/variants/glassway/overridetree.cb | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb index 7a12c29f4c..7f0aed45f8 100644 --- a/src/mainboard/google/brya/variants/glassway/overridetree.cb +++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb @@ -403,10 +403,13 @@ chip soc/intel/alderlake register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "100" - register "generic.reset_off_delay_ms" = "2" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "4" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "6" + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "105" + register "generic.stop_off_delay_ms" = "5" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 41 on