diff --git a/src/mainboard/intel/Clearwater/Config b/src/mainboard/intel/Clearwater/Config new file mode 100644 index 0000000000..63783a266e --- /dev/null +++ b/src/mainboard/intel/Clearwater/Config @@ -0,0 +1,299 @@ + +## Set all of the defaults for an x86 architecture +## +arch i386 + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/i386/entry16.inc +mainboardinit cpu/i386/entry32.inc +ldscript cpu/i386/entry16.lds +ldscript cpu/i386/entry32.lds + +## +## Test for logical cpu thats not BSP +## This is hyperthreading! +## it may break! +## +#mainboardinit cpu/i786/logical_cpu.inc + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +mainboardinit cpu/i386/reset16.inc +ldscript cpu/i386/reset16.lds + +#mainboardinit mainboard/intel/sv2/reset32.inc +#ldscript mainboard/intel/sv2/reset32.lds + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript arch/i386/lib/id.lds + +## +## Startup code for secondary CPUS +## +#mainboardinit arch/i386/smp/secondary.inc +#mainboardinit arch/i386/lib/cpu_reset.inc + +## This is the early phase of linuxBIOS startup +## Things are delicate and we test to see if we should +## failover to another image. + +#mainboardinit northbridge/intel/82860/reset_test.inc +#mainboardinit arch/i386/lib/noop_failover.inc USE_NORMAL_IMAGE +#mainboardinit southbridge/intel/82801/cmos_failover.inc USE_FALLBACK_IMAGE +#ldscript arch/i386/lib/failover.lds USE_FALLBACK_IMAGE + +### +### O.k. We aren't just an intermediary anymore! +### + + +## +## Setup our mtrrs +## +#mainboardinit cpu/i786/earlymtrr.inc + +## +## TESTING!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +## +mainboardinit mainboard/intel/Clearwater/preserial.inc + +## +## Setup the serial port +## +mainboardinit superio/winbond/w83627hf/setup_serial.inc +#mainboardinit superio/winbond/w83627hf/setup_led.inc +mainboardinit pc80/serial.inc +mainboardinit arch/i386/lib/console.inc + +## +## Switch temporarily into C code to setup RAM +## +#mainboardinit cpu/i786/cache_ram_init.inc +#mainboardinit cpu/i786/cache_ram_test.inc +#mainboardinit cpu/i786/cache_ram_start.inc +#mainboardinit cpu/i786/cache_ram_fini.inc +#ldscript cpu/i786/cache_ram.lds + +mainboardinit ram/ramtest.inc +option RAMTEST=1 +#mainboardinit ram/dump_northbridge.inc +mainboardinit mainboard/intel/Clearwater/dumpdev.inc + +## +## Setup RAM +## +mainboardinit southbridge/intel/82801ca/smbus.inc +mainboardinit southbridge/intel/82801ca/smbus_read_block.inc +mainboardinit southbridge/intel/82801ca/smbus_noop_read_block.inc +mainboardinit southbridge/intel/82801ca/smbus_read_byte.inc +#mainboardinit sdram/generic_dump_spd.inc + + +## +## Include the secondary Configuration files +## +northbridge intel/E7500 +southbridge intel/82801ca +southbridge intel/82870 +#nsuperio NSC/pc87309 com1={1} com2={1} floppy=1 lpt=1 keyboard=1 +nsuperio winbond/w83627hf com1={1} com2={1} floppy=1 lpt=1 keyboard=1 +dir /src/pc80 +dir /src/superio/winbond/w83627hf +dir /src/ram/ +cpu p5 +cpu p6 +cpu i786 + +## +## We'll need a udelay function +## + +option CONFIG_UDELAY_TSC=1 + +## +## Build the objects we have code for in this directory. +## +object mainboard.o +#object mtrr_values.o +object mptable.o HAVE_MP_TABLE +object irq_tables.o HAVE_PIRQ_TABLE + + +### +### Build options +### + +## +## Location of the DIMM EEPROMS on the SMBUS +## This is fixed into a narrow range by the DIMM package standard. +## +option SMBUS_MEM_CHANNEL_OFF=4 +option SMBUS_MEM_DEVICE_START=(0xa << 3) +option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +2) +option SMBUS_MEM_DEVICE_INC=1 + +## +## Customize our winbond superio chip for this motherboard +## +#option SIO_BASE=0x2e +#option SIO_SYSTEM_CLK_INPUT=SIO_SYSTEM_CLK_INPUT_48MHZ + +## +## Build code for the fallback boot +## +#option HAVE_FALLBACK_BOOT=1 + +## +## Build code for using cache as RAM +## +#option USE_CACHE_RAM=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +option HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +option HAVE_PIRQ_TABLE=1 + + +## +## Do not build special code to the keyboard +## +option NO_KEYBOARD=1 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +option HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option tabe table +## +#option HAVE_OPTION_TABLE=1 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +option SMP=1 +option MAX_CPUS=4 +option MAX_PHYSICAL_CPUS=2 + +## +## Build code to setup a generic IOAPIC +## +option IOAPIC=1 + +## +## MEMORY_HOLE instructs earlymtrr.inc to +## enable caching from 0-640KB and to disable +## caching from 640KB-1MB using fixed MTRRs +## +## Enabling this option breaks SMP because secondary +## CPU identification depends on only variable MTRRs +## being enabled. +## +nooption MEMORY_HOLE + +## +## Don't do a generic MTRR setup +## Instead use values from the fixed_mtrr_values array +## +#option HAVE_MTRR_TABLE=1 + +## +## Enable both fixed and variable MTRRS +## When we setup MTRRs in mtrr.c +## +## We must setup the fixed mtrrs or we confuse SMP secondary +## processor identification +## +#option ENABLE_FIXED_AND_VARIABLE_MTRRS=1 + + +## +## Figure out which type of linuxBIOS image to build +## If we aren't a fallback image we must be a normal image +## This is useful for optional includes +## +option USE_FALLBACK_IMAGE=0 +expr USE_NORMAL_IMAGE=!USE_FALLBACK_IMAGE + +### +### LinuxBIOS layout values +### + +## ROM_SIZE is the size of boot ROM that this board will use. +option ROM_SIZE=1048576 + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +option ROM_IMAGE_SIZE=65536 + +## LinuxBIOS C code runs at this location in RAM +option _RAMBASE=0x00008000 + +## For the trick of using cache as ram +## put the fake ram location at this address +option CACHE_RAM_BASE=0xfff70000 +option CACHE_RAM_SIZE=0x00010000 + +## +## Use a small 8K stack +## +option STACK_SIZE=0x2000 + +## +## Use a small 8K heap +## +option HEAP_SIZE=0x2000 + +## +## Clean up the motherboard id strings +## +option MAINBOARD_PART_NUMBER=Clearwater +option MAINBOARD_VENDOR=Intel + +option PYRO_SERIAL=1 + +## +## Only use the option table in a normal image +## +#expr USE_OPTION_TABLE=!USE_FALLBACK_IMAGE + +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +expr ROM_SECTION_SIZE =(USE_FALLBACK_IMAGE*65536)+(USE_NORMAL_IMAGE*(ROM_SIZE - 65536)) +expr ROM_SECTION_OFFSET=(USE_FALLBACK_IMAGE*(ROM_SIZE-65536))+(USE_NORMAL_IMAGE*0) + + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +expr ZKERNEL_START =(0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +expr PAYLOAD_SIZE =ROM_SECTION_SIZE - ROM_IMAGE_SIZE + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +#expr _ROMBASE =ZKERNEL_START + PAYLOAD_SIZE +expr _ROMBASE = 0xffff0000 - (USE_FALLBACK_IMAGE*0x10000) + +## +## Compute a range of ROM that can cached to speed of linuxBIOS, +## execution speed. +## +expr XIP_ROM_SIZE = 65536 +expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE diff --git a/src/mainboard/intel/Clearwater/defines b/src/mainboard/intel/Clearwater/defines new file mode 100644 index 0000000000..1a3be2d4ce --- /dev/null +++ b/src/mainboard/intel/Clearwater/defines @@ -0,0 +1,40 @@ +#define S0_WAIT() \ + movw $0x3fd, %dx ;\ +9: inb %dx, %al ;\ + test $0x40, %al ;\ + je 9b + +#define S0_EMIT(char) \ +9: movw $0x3fd, %dx ;\ + inb %dx, %al ;\ + test $0x20, %al ;\ + je 9b ;\ + movb $char,%al ;\ + movw $0x3f8, %dx ;\ + outb %al, %dx + +#define __CONSOLE_INLINE_TX_HEX8(byte) \ + movb byte, %al ; \ + shr $4, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + movw $0x3f8, %dx ;\ + outb %al, %dx ;\ +10: movw $0x3fd, %dx ;\ + inb %dx, %al ;\ + test $0x20, %al ;\ + je 10b ;\ + movw $0x3f8, %dx ;\ + mov byte, %al ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + movw $0x3f8, %dx ;\ + outb %al, %dx + diff --git a/src/mainboard/intel/Clearwater/dumpdev.inc b/src/mainboard/intel/Clearwater/dumpdev.inc new file mode 100644 index 0000000000..a9d8586251 --- /dev/null +++ b/src/mainboard/intel/Clearwater/dumpdev.inc @@ -0,0 +1,65 @@ + /* Dump the first 64 longs for devfn 0, bus 0 + * i.e. the north bridge. + */ + +#define CS_WRITE_BYTE(addr, byte) \ + movl $addr, %eax ; \ + movl $byte, %edx ; \ + PCI_WRITE_CONFIG_BYTE + +#define CS_WRITE_WORD(addr, word) \ + movl $addr, %eax ; \ + movl $word, %ecx ; \ + PCI_WRITE_CONFIG_WORD + +#define CS_WRITE_LONG(addr, dword) \ + movl $addr, %eax ; \ + movl $dword, %ecx ; \ + PCI_WRITE_CONFIG_DWORD + +#define DEVFN(device, function) (((device) << 3) + (function)) +#ifndef CONFIG_ADDR +#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where)) +#endif + + jmp dumpdev_skip + .section ".rom.data" + +dd_banner: .string "dump device: " +dd_ret: .string "\r\n" +dd_done: .string "Done.\r\n" +dd_before: .string "Before setting values: \r\n" +dd_after: .string "After setting values: \r\n" + .previous + +# expects device devfn in %ecx + +dumpdev: + mov %esp, %ebp +# CONSOLE_INFO_TX_STRING($dd_banner) + CONSOLE_INFO_TX_HEX32(%ecx) + CONSOLE_INFO_TX_STRING($dd_ret) +# xorl %ecx, %ecx +1: + CONSOLE_INFO_TX_HEX8(%cl) + CONSOLE_INFO_TX_CHAR($':') + CONSOLE_INFO_TX_CHAR($' ') + +2: + movl %ecx, %eax + PCI_READ_CONFIG_BYTE + CONSOLE_INFO_TX_HEX8(%al) + CONSOLE_INFO_TX_CHAR($' ') + + incl %ecx + testb $0xf, %cl + jnz 2b + + CONSOLE_INFO_TX_CHAR($'\r') + CONSOLE_INFO_TX_CHAR($'\n') + cmpb $0, %cl + jne 1b + CONSOLE_INFO_TX_STRING($dd_done) + mov %ebp, %esp + RETSP +dumpdev_skip: diff --git a/src/mainboard/intel/Clearwater/example-fallback.config b/src/mainboard/intel/Clearwater/example-fallback.config new file mode 100644 index 0000000000..362c375515 --- /dev/null +++ b/src/mainboard/intel/Clearwater/example-fallback.config @@ -0,0 +1,104 @@ +## This will make a target directory of ./fallback +## This is relative to where the configuration file resides in the filesystem +target ./fallback + +mainboard supermicro/p4dc6 + +## Build a fallback not a normal image. +option USE_FALLBACK_IMAGE=1 + +## Build an image for a 512KB rom +## ./fallback/romimage is just the last 64KB which we reserve for the fallback image. +option ROM_SIZE=524288 +#option ROM_SIZE=1048576 + +## Select the maximum size the linuxBIOS code can compile to. +## Allow linuxBIOS to be up to 48KB in size +option ROM_IMAGE_SIZE=49152 + + +## +### The Serial Console +## +## Hardware flow control is currently ignored. + +## Enable the Serial Console +option SERIAL_CONSOLE=1 + +## Select the serial console baud rate. +option TTYS0_BAUD=115200 +#option TTYS0_BAUD=57600 +#option TTYS0_BAUD=38400 +#option TTYS0_BAUD=19200 +#option TTYS0_BAUD=9600 +#option TTYS0_BAUD=4800 +#option TTYS0_BAUD=2400 +#option TTYS0_BAUD=1200 + +# Select the serial console base port +option TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +option TTYS0_LCS=0x3 + + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +option DEFAULT_CONSOLE_LOGLEVEL=9 +## At a maximum only compile in this level of debugging +option MAXIMUM_CONSOLE_LOGLEVEL=6 + +## Use the elf bootloader +option USE_ELF_BOOT=1 + +## Select the boot device +option USE_GENERIC_ROM=1 +#option BOOT_FLOPPY=1 +#option USE_SERIAL_FILL_INBUF=1 +#option BOOT_IDE=1 + +# Load etherboot with the elf bootloader +# The payload command is relative the build directory +# So .. is the directory this config file resides in +payload ../eepro100.ebi + + +## +## Cpu Speed +## +option CPU_CLOCK_MULTIPLIER=XEON_X8 +#option CPU_CLOCK_MULTIPLIER=XEON_X9 +#option CPU_CLOCK_MULTIPLIER=XEON_X10 +#option CPU_CLOCK_MULTIPLIER=XEON_X11 +#option CPU_CLOCK_MULTIPLIER=XEON_X12 +#option CPU_CLOCK_MULTIPLIER=XEON_X13 +#option CPU_CLOCK_MULTIPLIER=XEON_X14 +#option CPU_CLOCK_MULTIPLIER=XEON_X15 +#option CPU_CLOCK_MULTIPLIER=XEON_X16 +#option CPU_CLOCK_MULTIPLIER=XEON_X17 +#option CPU_CLOCK_MULTIPLIER=XEON_X18 +#option CPU_CLOCK_MULTIPLIER=XEON_X19 +#option CPU_CLOCK_MULTIPLIER=XEON_X19 +#option CPU_CLOCK_MULTIPLIER=XEON_X20 +#option CPU_CLOCK_MULTIPLIER=XEON_X21 +#option CPU_CLOCK_MULTIPLIER=XEON_X22 +#option CPU_CLOCK_MULTIPLIER=XEON_X23 + +## +## Select power on after power fail setting +option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON +#option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON + diff --git a/src/mainboard/intel/Clearwater/example-normal.config b/src/mainboard/intel/Clearwater/example-normal.config new file mode 100644 index 0000000000..0ce189d2bf --- /dev/null +++ b/src/mainboard/intel/Clearwater/example-normal.config @@ -0,0 +1,105 @@ +## This will make a target directory of ./normal +## This is relative to where the configuration file resides in the filesystem +target ./normal + +mainboard supermicro/p4dc6 + +## Build a normal not a fallback image. +option USE_FALLBACK_IMAGE=0 + +## Build an image for a 512KB rom +## ./normal/romimage is the entire rom image except for the last 64KB +## which are reserved for the fallback image. +option ROM_SIZE=524288 +#option ROM_SIZE=1048576 + +## Select the maximum size the linuxBIOS code can compile to. +## Allow linuxBIOS to be up to 48KB in size +option ROM_IMAGE_SIZE=49152 + + +## +### The Serial Console +## +## Hardware flow control is currently ignored. + +## Enable the Serial Console +option SERIAL_CONSOLE=1 + +## Select the serial console baud rate. +option TTYS0_BAUD=115200 +#option TTYS0_BAUD=57600 +#option TTYS0_BAUD=38400 +#option TTYS0_BAUD=19200 +#option TTYS0_BAUD=9600 +#option TTYS0_BAUD=4800 +#option TTYS0_BAUD=2400 +#option TTYS0_BAUD=1200 + +# Select the serial console base port +option TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +option TTYS0_LCS=0x3 + + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +option DEFAULT_CONSOLE_LOGLEVEL=9 +## At a maximum only compile in this level of debugging +option MAXIMUM_CONSOLE_LOGLEVEL=8 + +## Use the elf bootloader +option USE_ELF_BOOT=1 + +## Select the boot device +option USE_GENERIC_ROM=1 +#option BOOT_FLOPPY=1 +#option USE_SERIAL_FILL_INBUF=1 +#option BOOT_IDE=1 + +# Load etherboot with the elf bootloader +# The payload command is relative the build directory +# So .. is the directory this config file resides in +payload ../eepro100.ebi + + +## +## Cpu Speed +## +#option CPU_CLOCK_MULTIPLIER=XEON_X8 +#option CPU_CLOCK_MULTIPLIER=XEON_X9 +#option CPU_CLOCK_MULTIPLIER=XEON_X10 +#option CPU_CLOCK_MULTIPLIER=XEON_X11 +#option CPU_CLOCK_MULTIPLIER=XEON_X12 +#option CPU_CLOCK_MULTIPLIER=XEON_X13 +#option CPU_CLOCK_MULTIPLIER=XEON_X14 +#option CPU_CLOCK_MULTIPLIER=XEON_X15 +#option CPU_CLOCK_MULTIPLIER=XEON_X16 +option CPU_CLOCK_MULTIPLIER=XEON_X17 +#option CPU_CLOCK_MULTIPLIER=XEON_X18 +#option CPU_CLOCK_MULTIPLIER=XEON_X19 +#option CPU_CLOCK_MULTIPLIER=XEON_X19 +#option CPU_CLOCK_MULTIPLIER=XEON_X20 +#option CPU_CLOCK_MULTIPLIER=XEON_X21 +#option CPU_CLOCK_MULTIPLIER=XEON_X22 +#option CPU_CLOCK_MULTIPLIER=XEON_X23 + +## +## Select power on after power fail setting +option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON +#option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON + diff --git a/src/mainboard/intel/Clearwater/irq_tables.c b/src/mainboard/intel/Clearwater/irq_tables.c new file mode 100644 index 0000000000..ca38a7eafe --- /dev/null +++ b/src/mainboard/intel/Clearwater/irq_tables.c @@ -0,0 +1,41 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ + +#include + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*17, /* there can be total 17 devices on the bus */ + 0, /* Where the interrupt router lies (bus) */ + 0xf8, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0, /* Vendor */ + 0, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xd3, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + {0,0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0,0x10, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x1,0xe8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x2,0x8, {{0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}}, 0x2, 0}, + {0x2,0x10, {{0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}}, 0x3, 0}, + {0x1,0xf8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x3,0x8, {{0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}}, 0x1, 0}, + {0,0xe8, {{0x60, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0,0xe9, {{0, 0xdef8}, {0x63, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0,0xf0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x4,0x8, {{0x61, 0xdcb8}, {0x62, 0xdcb8}, {0x61, 0xdcb8}, {0x62, 0xdcb8}}, 0x4, 0}, + {0x4,0x10, {{0x63, 0xdcb8}, {0x60, 0xdcb8}, {0x63, 0xdcb8}, {0x60, 0xdcb8}}, 0x5, 0}, + {0x4,0x18, {{0x69, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x4,0x20, {{0x68, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x4,0x28, {{0x6b, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x4,0x30, {{0x6a, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0,0xfb, {{0, 0xdef8}, {0x61, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + } +}; diff --git a/src/mainboard/intel/Clearwater/mainboard.c b/src/mainboard/intel/Clearwater/mainboard.c new file mode 100644 index 0000000000..88223cca77 --- /dev/null +++ b/src/mainboard/intel/Clearwater/mainboard.c @@ -0,0 +1,255 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +// #include +#include +#include +#include +#include +// #include +#include + + +#define SMBUS_MEM_DEVICE_0 (0xa << 3) +extern int rdram_chips; /* number of ram chips on the rimms */ + + +unsigned long initial_apicid[MAX_CPUS] = +{ + 0, 6, 1, 7 +}; + +#ifndef CPU_CLOCK_MULTIPLIER +#define CPU_CLOCK_MULTIPLIER XEON_X17 +#endif + +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_OFF 2 + +#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + +#if 0 +void dump_pci_dev(int bus, int dev, int fn) +{ + + unsigned int offset = 0x80000000; + unsigned int i; + unsigned short devfn; + unsigned char byte; + + devfn = (dev <<3) | fn; + offset |= (bus << 16) | (devfn << 8); + + printk_notice("dump %u:%u.%u:\n", bus,dev,fn); + + for(i=0; i<256; i++) { + + if(! (i & 0x0f)) + printk_notice( "\n%02x: ", i); + + pcibios_read_config_byte(bus, devfn, i, &byte); + printk_notice( "%02x ", byte); + } + + printk_notice("\nDone.\n\n"); + +} + +#endif + + + + + +static void set_power_on_after_power_fail(int setting) +{ + switch(setting) { + case MAINBOARD_POWER_ON: + default: + ich3_power_after_power_fail(1); +// w832627hf_power_after_power_fail(POWER_ON); + break; + case MAINBOARD_POWER_OFF: + ich3_power_after_power_fail(0); +// w832627hf_power_after_power_fail(POWER_OFF); + break; + + } +} + +static void set_thermal_monitoring(int thermal_monitoring) +{ + int tm_high,tm_low; + + rdmsr(MISC_ENABLE,tm_low,tm_high); + if(thermal_monitoring != THERMAL_MONITORING_OFF) { + tm_low |= THERMAL_MONITORING_SET; + } + else { + tm_low &= ~THERMAL_MONITORING_SET; + } + wrmsr(MISC_ENABLE,tm_low,tm_high); + return; +} + +void mainboard_fixup(void) +{ + int cpu_clock_multiplier; + int power_on_after_power_fail; + int thermal_monitoring; + + printk_notice("CW2 mainboard fixup:\n"); + ich3_enable_ioapic(); + p64h2_enable_ioapic(); + ich3_enable_serial_irqs(); + ich3_enable_ide(1,1); + // test, SMJ +// ich3_rtc_init(); + ich3_lpc_route_dma(0xff); + isa_dma_init(); + ich3_1e0_misc(); + ich3_1f0_misc(); + + // SMJ dump some registers! +#if 0 + dump_pci_dev(0, 0, 0); + + printk_notice("1st bridge:\n"); + dump_pci_dev(0, 3, 0); + + + printk_notice("APIC:\n"); + dump_pci_dev(1, 0x1c, 0); + dump_pci_dev(1, 0x1e, 0); + + printk_notice("bridge:\n"); + dump_pci_dev(1, 0x1d, 0); + dump_pci_dev(1, 0x1f, 0); + + printk_notice("ether (connected to 1:0x1f.0):\n"); + dump_pci_dev(3, 0x7, 0); + dump_pci_dev(3, 0x7, 1); +#endif + + // test only SMJ + return; + + cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER; + if(get_option(&cpu_clock_multiplier, "CPU_clock_speed")) + cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER; + ich3_set_cpu_multiplier(cpu_clock_multiplier); + + power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + if(get_option(&power_on_after_power_fail, "power_on_after_power_fail")) + power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + set_power_on_after_power_fail(power_on_after_power_fail); + + thermal_monitoring = THERMAL_MONITORING_OFF; + if(get_option(&thermal_monitoring, "thermal_monitoring")) + thermal_monitoring = THERMAL_MONITORING_OFF; + set_thermal_monitoring(thermal_monitoring); + + return; +} + +void hard_reset(void) +{ + ich3_hard_reset(); +} + +#ifdef USE_CACHE_RAM + +void cache_ram_start(void) +{ + int error; + + error = 0; + /* displayinit MUST PRECEDE ALL PRINTK! */ + +#if 1 + displayinit(); +#endif + printk_info("Finding PCI configuration type.\n"); + pci_set_method(); + printk_info("Setting up smbus controller\n"); + smbus_setup(); + ich3_rtc_init(); + printk_info("Selecting rdram i2c bus\n"); +// select_rdram_i2c(); + +#if 0 + display_smbus_spd(); +#endif + + init_memory(); + +#if 0 + { + unsigned long addr; + for(addr = 0; addr < 0x20000000; addr += 0x02000000) { + ram_fill(addr, addr + 0x400); + } + /* Do some dummy writes to flush a write cache, in the + * processor. + */ + ram_fill(0xc0000000, 0xc0000400); + for(addr = 0; addr < 0x20000000; addr += 0x02000000) { + ram_verify(addr, addr + 0x400, 1); + } + } +#endif +#if 1 + printk_debug("starting ramcheck\n"); + error |= ramcheck(0x00000000, 0x00080000, 40); + error |= ramcheck(0x02000000, 0x02080000, 40); + error |= ramcheck(0x04000000, 0x04080000, 40); + error |= ramcheck(0x06000000, 0x06080000, 40); + error |= ramcheck(0x08000000, 0x08080000, 40); + error |= ramcheck(0x0a000000, 0x0a080000, 40); + error |= ramcheck(0x0c000000, 0x0c080000, 40); + error |= ramcheck(0x0e000000, 0x0e080000, 40); + error |= ramcheck(0x1a000000, 0x1a080000, 40); +#if 0 + error |= ramcheck(0x10000000, 0x10080000, 20); + error |= ramcheck(0x12000000, 0x12080000, 20); + error |= ramcheck(0x14000000, 0x14080000, 20); + error |= ramcheck(0x16000000, 0x16080000, 20); + error |= ramcheck(0x18000000, 0x18080000, 20); + error |= ramcheck(0x1a000000, 0x1a080000, 20); + error |= ramcheck(0x1c000000, 0x1c080000, 20); + error |= ramcheck(0x1e000000, 0x1e080000, 20); +#endif +#endif +#if 0 + error |= ramcheck(0x00000000, 0x00080000, 20); +#endif +#if 0 + display_rdram_regs(rdram_chips ); +#endif +#if 0 + display_mch_regs(); +#endif + if (error) { + printk_err("Something isn't working!!!\n"); + while(1); + } else { + printk_info("Leaving cacheram...\n"); + } + +} + + +#endif + + + diff --git a/src/mainboard/intel/Clearwater/mptable.c b/src/mainboard/intel/Clearwater/mptable.c new file mode 100644 index 0000000000..5478598dd2 --- /dev/null +++ b/src/mainboard/intel/Clearwater/mptable.c @@ -0,0 +1,161 @@ +/* generatred by MPTable, version 2.0.15*/ +/* as modified by RGM for LinuxBIOS */ +#include +#include +#include +#include +#include + +void *smp_write_config_table(void *v, unsigned long * processor_map) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "LnxLabs "; + static const char productid[12] = "Clearwater "; + struct mp_config_table *mc; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + +#if 0 + smp_write_processor(mc, 0x00, 0x14, CPU_BOOTPROCESSOR | CPU_ENABLED, + 0x00000f24, 0x3febfbff); + smp_write_processor(mc, 0x06, 0x14, CPU_ENABLED, 0x00000f24, 0x3febfbff); + smp_write_processor(mc, 0x01, 0x14, CPU_ENABLED, 0x00000f24, 0x3febfbff); + smp_write_processor(mc, 0x07, 0x14, CPU_ENABLED, 0x00000f24, 0x3febfbff); +#else + smp_write_processors(mc, processor_map); +#endif + + +/*Bus: Bus ID Type*/ + smp_write_bus(mc, 0, "PCI "); + smp_write_bus(mc, 1, "PCI "); + smp_write_bus(mc, 2, "PCI "); + smp_write_bus(mc, 3, "PCI "); + smp_write_bus(mc, 4, "PCI "); + smp_write_bus(mc, 5, "ISA "); +/*I/O APICs: APIC ID Version State Address*/ + smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + { + struct pci_dev *dev; + uint32_t base; + dev = pci_find_slot(1, PCI_DEVFN(0x1e,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 3, 0x20, base); + } + dev = pci_find_slot(1, PCI_DEVFN(0x1c,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 4, 0x20, base); + } + dev = pci_find_slot(4, PCI_DEVFN(0x1e,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 5, 0x20, base); + } + dev = pci_find_slot(4, PCI_DEVFN(0x1c,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 8, 0x20, base); + } + } +/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# +*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x1, 0x2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x2, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x3, 0x2, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x4, 0x2, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x6, 0x2, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x7, 0x2, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x8, 0x2, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x9, 0x2, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xc, 0x2, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xd, 0x2, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xe, 0x2, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xf, 0x2, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0xc, 0x2, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x10, 0x2, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x14, 0x2, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x18, 0x2, 0x16); +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, MP_APIC_ALL, 0x1); +/* MP Config Extended Table Entries: + +-- +System Address Space + bus ID: 0 address type: I/O address + address base: 0x0 + address range: 0x10000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0x40000000 + address range: 0xbee00000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xfee01000 + address range: 0x11ff000 +-- +System Address Space + bus ID: 4 address type: memory address + address base: 0xa0000 + address range: 0x20000 +-- +System Address Space + bus ID: 4 address type: memory address + address base: 0xcc000 + address range: 0x10000 +-- +System Address Space + bus ID: 4 address type: memory address + address base: 0xe0000 + address range: 0x4000 +-- +Bus Heirarchy + bus ID: 5 bus info: 0x01 parent bus ID: 0-- +Compatibility Bus Address + bus ID: 0 address modifier: add + predefined range: 0x00000000-- +Compatibility Bus Address + bus ID: 0 address modifier: add + predefined range: 0x00000001 There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p +", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v, processor_map); +} diff --git a/src/mainboard/intel/Clearwater/mptable.c.intel b/src/mainboard/intel/Clearwater/mptable.c.intel new file mode 100644 index 0000000000..05f0d6da3e --- /dev/null +++ b/src/mainboard/intel/Clearwater/mptable.c.intel @@ -0,0 +1,168 @@ +/* generatred by MPTable, version 2.0.15*/ +/* as modified by RGM for LinuxBIOS */ +#include +#include +#include +#include +#include + +#define conforms MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH + +void *smp_write_config_table(void *v, unsigned long * processor_map) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "LNXI "; + static const char productid[12] = "P4DPE "; + struct mp_config_table *mc; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + +#if 1 + smp_write_processor(mc, 0x00, 0x14, CPU_BOOTPROCESSOR | CPU_ENABLED, + 0x00000f24, 0x3febfbff); + smp_write_processor(mc, 0x06, 0x14, CPU_ENABLED, 0x00000f24, 0x3febfbff); + smp_write_processor(mc, 0x01, 0x14, CPU_ENABLED, 0x00000f24, 0x3febfbff); + smp_write_processor(mc, 0x07, 0x14, CPU_ENABLED, 0x00000f24, 0x3febfbff); +#else + smp_write_processors(mc, processor_map); +#endif + + +/*Bus: Bus ID Type*/ + smp_write_bus(mc, 0, "PCI "); + smp_write_bus(mc, 1, "PCI "); + smp_write_bus(mc, 2, "PCI "); + smp_write_bus(mc, 3, "PCI "); + smp_write_bus(mc, 4, "PCI "); + smp_write_bus(mc, 5, "ISA "); +/*I/O APICs: APIC ID Version State Address*/ + smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + { + struct pci_dev *dev; + uint32_t base; + dev = pci_find_slot(1, PCI_DEVFN(0x1e,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 3, 0x20, base); + } + dev = pci_find_slot(1, PCI_DEVFN(0x1c,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 4, 0x20, base); + } +// dev = pci_find_slot(4, PCI_DEVFN(0x1e,0)); +// if (dev) { +// pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); +// base &= PCI_BASE_ADDRESS_MEM_MASK; +// smp_write_ioapic(mc, 5, 0x20, base); +// } +// dev = pci_find_slot(4, PCI_DEVFN(0x1c,0)); +// if (dev) { +// pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); +// base &= PCI_BASE_ADDRESS_MEM_MASK; +// smp_write_ioapic(mc, 8, 0x20, base); +// } + } +/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# +*/ smp_write_intsrc(mc, mp_ExtINT, conforms|conforms, 0x5, 0x0, 0x8, 0x0); + smp_write_intsrc(mc, mp_INT, conforms|conforms, 0x5, 0x1, 0x8, 0x1); + smp_write_intsrc(mc, mp_INT, conforms|conforms, 0x5, 0x0, 0x8, 0x2); + smp_write_intsrc(mc, mp_INT, conforms|conforms, 0x5, 0x3, 0x8, 0x3); + smp_write_intsrc(mc, mp_INT, conforms|conforms, 0x5, 0x4, 0x8, 0x4); + smp_write_intsrc(mc, mp_INT, conforms|conforms, 0x5, 0x5, 0x8, 0x5); + smp_write_intsrc(mc, mp_INT, conforms|conforms, 0x5, 0x6, 0x8, 0x6); + smp_write_intsrc(mc, mp_INT, conforms|conforms, 0x5, 0x7, 0x8, 0x7); + smp_write_intsrc(mc, mp_INT, conforms|conforms, 0x5, 0x8, 0x8, 0x8); + smp_write_intsrc(mc, mp_INT, conforms|conforms, 0x5, 0x9, 0x8, 0x9); + smp_write_intsrc(mc, mp_INT, conforms|conforms, 0x5, 0xa, 0x8, 0xa); + smp_write_intsrc(mc, mp_INT, conforms|conforms, 0x5, 0xb, 0x8, 0xb); + smp_write_intsrc(mc, mp_INT, conforms|conforms, 0x5, 0xc, 0x8, 0xc); + smp_write_intsrc(mc, mp_INT, conforms|conforms, 0x5, 0xd, 0x8, 0xd); + smp_write_intsrc(mc, mp_INT, conforms|conforms, 0x5, 0xe, 0x8, 0xe); + smp_write_intsrc(mc, mp_INT, conforms|conforms, 0x5, 0xf, 0x8, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x8, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x8, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x8, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x30, 0x8, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x1c, 0x9, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x1d, 0x9, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x20, 0x9, 0x0); +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1); + +/* +MP Config Extended Table Entries: + +-- +System Address Space + bus ID: 0 address type: I/O address + address base: 0x0 + address range: 0x4000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0x40000000 + address range: 0xbc900000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xfc900000 + address range: 0x2300000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xfec00000 + address range: 0x100000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xff000000 + address range: 0x1000000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xa0000 + address range: 0x20000 +-- +Bus Heirarchy + bus ID: 5 bus info: 0x01 parent bus ID: 0-- +Compatibility Bus Address + bus ID: 0 address modifier: add + predefined range: 0x00000000-- +Compatibility Bus Address + bus ID: 0 address modifier: add + predefined range: 0x00000001 /* There is no extension information... */ + + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p ", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v, processor_map); +} diff --git a/src/mainboard/intel/Clearwater/mtrr_values.c b/src/mainboard/intel/Clearwater/mtrr_values.c new file mode 100644 index 0000000000..68c1a6eefc --- /dev/null +++ b/src/mainboard/intel/Clearwater/mtrr_values.c @@ -0,0 +1,49 @@ +#include + +/* We want to cache memory as efficiently as possible. + */ +#define RAM MTRR_TYPE_WRBACK +/* We can't use Write Combining on a legacy frame buffer because + * it is incompatible with EGA 16 color video modes... + */ +#define FB MTRR_TYPE_UNCACHABLE +/* For areas that are supposed to cover roms it makes no + * sense to cache writes. + */ +#define ROM MTRR_TYPE_WRPROT + + +unsigned char fixed_mtrr_values[][4] = { + /* MTRRfix64K_00000_MSR, defines memory range from 0KB to 512 KB, each byte cover 64KB area */ + {RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM}, + + /* MTRRfix16K_80000_MSR, defines memory range from 512KB to 640KB, each byte cover 16KB area */ + {RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM}, + + /* MTRRfix16K_A0000_MSR, defines memory range from A0000 to C0000, each byte cover 16KB area */ + {FB, FB, FB, FB}, {FB, FB, FB, FB}, + + /* MTRRfix4K_C0000_MSR, defines memory range from C0000 to C8000, each byte cover 4KB area */ + {RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM}, + + /* MTRRfix4K_C8000_MSR, defines memory range from C8000 to D0000, each byte cover 4KB area */ + {RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM}, + + /* MTRRfix4K_D0000_MSR, defines memory range from D0000 to D8000, each byte cover 4KB area */ + {RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM}, + + /* MTRRfix4K_D8000_MSR, defines memory range from D8000 to E0000, each byte cover 4KB area */ + {RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM}, + + /* MTRRfix4K_E0000_MSR, defines memory range from E0000 to E8000, each byte cover 4KB area */ + {RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM}, + + /* MTRRfix4K_E8000_MSR, defines memory range from E8000 to F0000, each byte cover 4KB area */ + {RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM}, + + /* MTRRfix4K_F0000_MSR, defines memory range from F0000 to F8000, each byte cover 4KB area */ + {RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM}, + + /* MTRRfix4K_F8000_MSR, defines memory range from F8000 to 100000, each byte cover 4KB area */ + {RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM}, +}; diff --git a/src/mainboard/intel/Clearwater/preserial.inc b/src/mainboard/intel/Clearwater/preserial.inc new file mode 100644 index 0000000000..fd6f8a5e02 --- /dev/null +++ b/src/mainboard/intel/Clearwater/preserial.inc @@ -0,0 +1,458 @@ + jmp preserial + + +#define S0_WAIT() \ + movw $0x3fd, %dx ;\ +9: inb %dx, %al ;\ + test $0x40, %al ;\ + je 9b + +#define S0_EMIT(char) \ +9: movw $0x3fd, %dx ;\ + inb %dx, %al ;\ + test $0x20, %al ;\ + je 9b ;\ + movb $char,%al ;\ + movw $0x3f8, %dx ;\ + outb %al, %dx + +#define __CONSOLE_INLINE_TX_HEX8(byte) \ + movb byte, %al ; \ + shr $4, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + movw $0x3f8, %dx ;\ + outb %al, %dx ;\ +10: movw $0x3fd, %dx ;\ + inb %dx, %al ;\ + test $0x20, %al ;\ + je 10b ;\ + movw $0x3f8, %dx ;\ + mov byte, %al ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + movw $0x3f8, %dx ;\ + outb %al, %dx + +southbridge_table_start: + + .byte 0x01, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00 # 40 + .byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00 # 50 + .byte 0x0a, 0x0b, 0x80, 0x09, 0xd1, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00 # 60 + .byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # 70 + .byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # 80 + .byte 0xff, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # 90 + .byte 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # a0 + .byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # b0 + .byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # c0 + .byte 0x86, 0x39, 0x00, 0x00, 0x02, 0x0f, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # d0 + .byte 0x10, 0x00, 0x00, 0xc0, 0x00, 0xa0, 0x0f, 0x1c, 0x33, 0x22, 0x11, 0x00, 0x00, 0x00, 0x67, 0x45 # e0 + .byte 0x0f, 0x00, 0x60, 0x84, 0x00, 0x00, 0x00, 0x00, 0x47, 0x0f, 0x0e, 0x00, 0x00, 0x00, 0x81, 0x00 # f0 + +southbridge_end: + +.globl preserial + preserial: + + .code32 + + cli + +#call off the dog + movw $0x461, %dx + movb $0x20, %al + outb %al, %dx + dec %dx + movb $0x01, %al + outb %al, %dx + + movl $0x8000f8d4, %eax + movw $0xcf8, %dx + outl %eax, %dx + movw $0xcfc, %dx + movb $0x2, %al +# movb $0x0, %al # 0x02 here to disable watchdog function + outb %al, %dx + +# movw $0x468, %dx +# movw $0x800, %ax +# outw %ax, %dx +# + +#turn on LPC I/o access to superio + movl $0x8000f8e6, %eax + mov $0xcf8, %dx + outl %eax, %dx + + mov $0xcfc, %dx + movw $0x1c0f, %ax + outw %ax, %dx + +#assign i/o ranges for serial I/O + movl $0x8000f8e0, %eax + mov $0xcf8, %dx + outl %eax, %dx + + mov $0xcfc, %dx + mov $0x10, %al + outb %al, %dx + +#attempt to get Natsemi superio to ID itself +#movw $0x2e, %dx +#movb $0x20, %al +#outb %al, %dx + +#inc %dx +#inb %dx, %al + +#cmp $0x0ee, %al +#je corrupt_cmos + + #OK, now, lets turn serial on! + + jmp noreset + #first, reset the serial chip to defaults + movw $0x2e, %dx + movb $0x21, %al + outb %al, %dx + + inc %dx + movb $0x13, %al + outb %al, %dx + +noreset: + movw $0x2e, %dx + movb $0x21, %al + outb %al, %dx + + inc %dx + movb $0x19, %al + outb %al, %dx + + dec %dx + movb $0x22, %al + outb %al, %dx + inc %dx + outb %al, %dx # YES! 22->22 + + dec %dx + movb $0x23, %al + outb %al, %dx + inc %dx + movb $0x72, %al + outb %al, %dx + + dec %dx + movb $0x24, %al + outb %al, %dx + inc %dx + movb $0x26, %al + outb %al, %dx + + dec %dx + movb $0x2a, %al + outb %al, %dx + inc %dx + movb $0x0b, %al + outb %al, %dx + +#enable serial + dec %dx + movb $0x07, %al + outb %al, %dx + inc %dx + movb $0x03, %al + outb %al, %dx + + dec %dx + movb $0x30, %al + outb %al, %dx + inc %dx + movb $0x01, %al + outb %al, %dx + +#O.K. now lets try to set up serial part way, then confirm that its active + + #turn off serial interrupts, we have no vectors + movw $0x3f9, %dx + movb $0x0, %al + outb %al, %dx + + #set divisor to 115200 + movw $0x3fb, %dx + movb $0x83, %al + outb %al, %dx + + movw $0x3f8, %dx + movb $0x01, %al + outb %al, %dx + inc %dx + + movb $0x00, %al + outb %al, %dx + + #set n81 + movw $0x3fb, %dx + movb $0x03, %al + outb %al, %dx + + #FIFO setup $0xc7 -> 0x3fa + movw $0x3fa, %dx + movb $0xc7, %al + out %al, %dx + + + + #set DTR, RTS, OUT2 (whatever that is) + movw $0x3fc, %dx + movb $0xb, %al + outb %al, %dx + + jmp preserial_out + +#set null descriptor to all but CS +#movw $0x0, %ax +#movw %ax, %ds +#movw %ax, %es +#movw %ax, %fs +#movw %ax, %gs + + S0_EMIT('C') + S0_EMIT('S') + S0_EMIT(':') + movw %cs, %ax + movw %ax, %bx + __CONSOLE_INLINE_TX_HEX8(%bh) + __CONSOLE_INLINE_TX_HEX8(%bl) + S0_EMIT('\r') + S0_EMIT('\n') + + S0_EMIT('D') + S0_EMIT('S') + S0_EMIT(':') + S0_WAIT() + movw %ds, %ax + movw %ax, %bx + __CONSOLE_INLINE_TX_HEX8(%bh) + __CONSOLE_INLINE_TX_HEX8(%bl) + S0_EMIT('\r') + S0_EMIT('\n') + + S0_EMIT('C') + S0_EMIT('R') + S0_EMIT('0') + S0_EMIT(':') + + S0_WAIT() + + movl %cr0, %eax + movl %eax, %ebx + movl %eax, %ecx + shr $0x16, %ebx + + __CONSOLE_INLINE_TX_HEX8(%bh) + __CONSOLE_INLINE_TX_HEX8(%bl) + movw %cx,%bx + + __CONSOLE_INLINE_TX_HEX8(%bh) + __CONSOLE_INLINE_TX_HEX8(%bl) + + S0_EMIT('\r') + S0_EMIT('\n') + + movl $0x10002, %esi +#sgdt %cs:(%esi) + sgdt (%esi) + + S0_EMIT('G') + S0_EMIT('D') + S0_EMIT('T') + S0_EMIT(':') + + movw (0x10002), %cx + movl (0x10004), %ebx + +out1: + __CONSOLE_INLINE_TX_HEX8( %cs:(%ebx) ) + inc %bx + dec %cx + jnz out1 + +#movw $0x4, %cx +#loop3: +#__CONSOLE_INLINE_TX_HEX8(%bl) +#shr $0x08, %ebx +#dec %cx +#jnz loop3 + + + #just a test, emit a PYRO + S0_EMIT('P') + + jmp dolgdt + + .align 4 +dolgdt: + lgdt %cs:gdtptr + S0_EMIT('Y') + ljmp $0x10,$csload +csload: + S0_EMIT('R') + + movw $0x18, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %fs + movw %ax, %gs + movw %ax, %ss + + S0_EMIT('O') + S0_EMIT('\r') + S0_EMIT('\n') + +#movb $0x50, %al +#movw $0x3f8, %dx +#outb %al, %dx +#movb $0x59, %al +#outb %al, %dx +#movb $0x52, %al +#outb %al, %dx +#movb $0x4f, %al +#outb %al, %dx + +#movb $0x0d, %al +#outb %al, %dx + +#movb $0x0a, %al +#outb %al, %dx + + + #indicate we did it by clearing DTR + movw $0x3fc, %dx + movb $0x0a, %al + outb %al, %dx + + + + jmp preserial_out + + movl $southbridge_table_start, %esi + movl $(southbridge_end - southbridge_table_start), %ecx + shrl $0x02, %ecx + movl $0x8000f840, %eax + movl %eax, %ebx + +next_dword: + movw $0xcf8, %dx + movl %ebx, %eax + outl %eax, %dx + inc %eax + inc %eax + inc %eax + inc %eax + movl %eax, %ebx + lodsl (%esi), %eax + movw $0xcfc, %dx + outl %eax, %dx + loopnz next_dword + + + jmp preserial_out + + + movl $0x8000f8e0, %eax + mov $0xcf8, %dx + outl %eax, %dx + + mov $0xcfc, %dx + mov $0x10, %al + outb %al, %dx + + + + jmp preserial_out + +corrupt_cmos: + mov $0x72, %dx + mov $0x50, %al + outb %al, %dx + inc %dx + mov $0x42, %al + outb %al, %dx + + dec %dx + mov $0x51, %al + outb %al, %dx + inc %dx + mov $0xbe, %al + outb %al, %dx + + +#now, strobe HD light a few times to prove we made it here + + mov $30, %bx + mov $0x480, %dx +again: + mov $0xa7, %al + outb %al, %dx + movl $0xfffffff,%ecx +loop1: + dec %ecx + jnz loop1 + + mov $0xa6, %al + outb %al, %dx + movl $0xfffffff,%ecx +loop2: + dec %ecx + jnz loop2 + + + dec %bx + jnz again + + +preserial_out: + + S0_EMIT('A') + S0_EMIT('P') + S0_EMIT('I') + S0_EMIT('C') + S0_EMIT('I') + S0_EMIT('D') + S0_EMIT(':') + + movl $APIC_DEFAULT_BASE, %edi + movl APIC_ID(%edi), %eax + shrl $24, %eax + + __CONSOLE_INLINE_TX_HEX8(%al) + S0_EMIT('\r') + S0_EMIT('\n') + + +#very temporary, set TOLM to 1 Gig. This should be enumerated or otherwise tested! + movl $0x800000c4, %eax + movw $0xcf8, %dx + outl %eax, %dx + movw $0x4000, %ax + movw $0xcfc, %dx + outw %ax, %dx + +#set PCI dev 0:0.0.e0 < 0x1e + movl $0x800000e0, %eax + movw $0xcf8, %dx + outl %eax, %dx + movb $0x1e, %al + movw $0xcfc, %dx + outb %al, %dx + +jmp console0 +