Correct some common spelling mistakes

- occured -> occurred
- accomodate -> accommodate
- existant -> existent
- asssertion -> assertion
- manangement -> management
- cotroller -> controller

Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12850
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/soc/broadcom/cygnus/ddr_init.c

@@ -1178,7 +1178,7 @@ static int clear_ddr(uint32_t offset, uint32_t size)
 	}
 	printk(BIOS_INFO, "clear_ddr: Failed: 0x%lx\n", get_timer(start));
 	if(reg32_read((volatile uint32_t *)DDR_BistErrorOccurred))
-		printk(BIOS_ERR, "clear_ddr: Error occured\n");
+		printk(BIOS_ERR, "clear_ddr: Error occurred\n");
 	return(1);
 }
 #endif /* CONFIG_IPROC_DDR_ECC */

src/soc/intel/braswell/smihandler.c

@@ -461,7 +461,7 @@ void southbridge_smi_handler(void)
 			southbridge_smi[i]();
 		} else {
 			printk(BIOS_DEBUG,
-			       "SMI_STS[%d] occured, but no "
+			       "SMI_STS[%d] occurred, but no "
 			       "handler available.\n", i);
 		}
 	}

src/soc/intel/skylake/smihandler.c

@@ -509,7 +509,7 @@ void southbridge_smi_handler(void)
 				southbridge_smi[i]();
 			} else {
 				printk(BIOS_DEBUG,
-				    "SMI_STS[%d] occured, but no handler available.\n",
+				    "SMI_STS[%d] occurred, but no handler available.\n",
 				    i);
 			}
 		}

src/soc/nvidia/tegra124/clock.c

@@ -389,7 +389,7 @@ clock_display(u32 frequency)
 
 /* Initialize the UART and put it on CLK_M so we can use it during clock_init().
  * Will later move it to PLLP in clock_config(). The divisor must be very small
- * to accomodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1
+ * to accommodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1
  * CLK_SOURCE divider to get more precision. (This might still not be enough for
  * some OSCs... if you use 13KHz, be prepared to have a bad time.) The 1900 has
  * been determined through trial and error (must lead to div 13 at 24MHz). */

src/soc/nvidia/tegra132/clock.c

@@ -389,7 +389,7 @@ u32 clock_configure_plld(u32 frequency)
 
 /* Initialize the UART and put it on CLK_M so we can use it during clock_init().
  * Will later move it to PLLP in clock_config(). The divisor must be very small
- * to accomodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1
+ * to accommodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1
  * CLK_SOURCE divider to get more precision. (This might still not be enough for
  * some OSCs... if you use 13KHz, be prepared to have a bad time.) The 1900 has
  * been determined through trial and error (must lead to div 13 at 24MHz). */