Correct some common spelling mistakes
- occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
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2e0d9447db
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2ed0aa258f
29 changed files with 58 additions and 58 deletions
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@ -45,7 +45,7 @@
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OperationRegion(K8TR, PCI_Config, 0xE4, 0x4)
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Field(K8TR, DWordAcc, NoLock, Preserve) {
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, 1,
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THTP, 1, /* Temperature sensor trip occured */
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THTP, 1, /* Temperature sensor trip occurred */
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CORE, 1, /* Select Core */
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TTS0, 1, /* Temperature sensor trip on CPU1 (or single core CPU0) */
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TTS1, 1, /* Temperature sensor trip on CPU0 */
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@ -275,7 +275,7 @@ static u32 GetScrubAddr_D(u32 Node)
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/* Scrub Addr High again, detect 32-bit wrap */
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val = Get_NB32(dev, reg);
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if(val != hi) {
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hi = val; /* Scrub Addr Low again, if wrap occured */
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hi = val; /* Scrub Addr Low again, if wrap occurred */
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lo = Get_NB32(dev, regx);
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}
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@ -2167,8 +2167,8 @@ static void sdram_program_clock_crossing(void)
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#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
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static const u32 data_clock_crossing[] = {
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0x00100401, 0x00000000, /* DDR400 FSB400 */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0x08040120, 0x00000000, /* DDR400 FSB533 */
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0x00100401, 0x00000000, /* DDR533 FSB533 */
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@ -2178,51 +2178,51 @@ static void sdram_program_clock_crossing(void)
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0x10040280, 0x00000040, /* DDR533 FSB667 */
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0x00100401, 0x00000000, /* DDR667 FSB667 */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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};
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static const u32 command_clock_crossing[] = {
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0x04020208, 0x00000000, /* DDR400 FSB400 */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0x00060108, 0x00000000, /* DDR400 FSB533 */
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0x04020108, 0x00000000, /* DDR533 FSB533 */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistent */
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0x00040318, 0x00000000, /* DDR400 FSB667 */
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0x04020118, 0x00000000, /* DDR533 FSB667 */
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0x02010804, 0x00000000, /* DDR667 FSB667 */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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};
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#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
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/* i945 G/P */
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static const u32 data_clock_crossing[] = {
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0x10080201, 0x00000000, /* DDR400 FSB533 */
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0x00100401, 0x00000000, /* DDR533 FSB533 */
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0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0x04020108, 0x00000000, /* DDR400 FSB800 */
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0x00020108, 0x00000000, /* DDR533 FSB800 */
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@ -2234,17 +2234,17 @@ static void sdram_program_clock_crossing(void)
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};
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static const u32 command_clock_crossing[] = {
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0x00010800, 0x00000402, /* DDR400 FSB533 */
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0x01000400, 0x00000200, /* DDR533 FSB533 */
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0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistant */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0xffffffff, 0xffffffff, /* nonexistent */
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0x02010804, 0x00000000, /* DDR400 FSB800 */
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0x00010402, 0x00000000, /* DDR533 FSB800 */
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@ -38,7 +38,7 @@ static void sdram_read_spds(struct sysinfo *s)
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int status = 0;
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FOR_EACH_DIMM(i) {
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if (s->spd_map[i] == 0) {
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/* Non-existant SPD address */
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/* Non-existent SPD address */
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s->dimms[i].card_type = 0;
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continue;
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}
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@ -36,7 +36,7 @@ static void vx900_print_sata_errors(u32 flags)
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printk(BIOS_DEBUG, "\tCOMWAKE %s\n",
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(flags & (1 << 16)) ? "detected" : "not detected");
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printk(BIOS_DEBUG, "\tExchange as determined by COMINIT %s\n",
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(flags & (1 << 26)) ? "occured" : "not occured");
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(flags & (1 << 26)) ? "occurred" : "not occurred");
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printk(BIOS_DEBUG, "\tPort selector presence %s\n",
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(flags & (1 << 27)) ? "detected" : "not detected");
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/* Errors */
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