Correct some common spelling mistakes

- occured -> occurred
- accomodate -> accommodate
- existant -> existent
- asssertion -> assertion
- manangement -> management
- cotroller -> controller

Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12850
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Martin Roth 2016-01-05 20:58:58 -07:00 committed by Stefan Reinauer
commit 2ed0aa258f
29 changed files with 58 additions and 58 deletions

View file

@ -45,7 +45,7 @@
OperationRegion(K8TR, PCI_Config, 0xE4, 0x4)
Field(K8TR, DWordAcc, NoLock, Preserve) {
, 1,
THTP, 1, /* Temperature sensor trip occured */
THTP, 1, /* Temperature sensor trip occurred */
CORE, 1, /* Select Core */
TTS0, 1, /* Temperature sensor trip on CPU1 (or single core CPU0) */
TTS1, 1, /* Temperature sensor trip on CPU0 */

View file

@ -275,7 +275,7 @@ static u32 GetScrubAddr_D(u32 Node)
/* Scrub Addr High again, detect 32-bit wrap */
val = Get_NB32(dev, reg);
if(val != hi) {
hi = val; /* Scrub Addr Low again, if wrap occured */
hi = val; /* Scrub Addr Low again, if wrap occurred */
lo = Get_NB32(dev, regx);
}

View file

@ -2167,8 +2167,8 @@ static void sdram_program_clock_crossing(void)
#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
static const u32 data_clock_crossing[] = {
0x00100401, 0x00000000, /* DDR400 FSB400 */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0x08040120, 0x00000000, /* DDR400 FSB533 */
0x00100401, 0x00000000, /* DDR533 FSB533 */
@ -2178,51 +2178,51 @@ static void sdram_program_clock_crossing(void)
0x10040280, 0x00000040, /* DDR533 FSB667 */
0x00100401, 0x00000000, /* DDR667 FSB667 */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
};
static const u32 command_clock_crossing[] = {
0x04020208, 0x00000000, /* DDR400 FSB400 */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0x00060108, 0x00000000, /* DDR400 FSB533 */
0x04020108, 0x00000000, /* DDR533 FSB533 */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistent */
0x00040318, 0x00000000, /* DDR400 FSB667 */
0x04020118, 0x00000000, /* DDR533 FSB667 */
0x02010804, 0x00000000, /* DDR667 FSB667 */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
};
#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
/* i945 G/P */
static const u32 data_clock_crossing[] = {
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0x10080201, 0x00000000, /* DDR400 FSB533 */
0x00100401, 0x00000000, /* DDR533 FSB533 */
0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0x04020108, 0x00000000, /* DDR400 FSB800 */
0x00020108, 0x00000000, /* DDR533 FSB800 */
@ -2234,17 +2234,17 @@ static void sdram_program_clock_crossing(void)
};
static const u32 command_clock_crossing[] = {
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0x00010800, 0x00000402, /* DDR400 FSB533 */
0x01000400, 0x00000200, /* DDR533 FSB533 */
0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0xffffffff, 0xffffffff, /* nonexistent */
0x02010804, 0x00000000, /* DDR400 FSB800 */
0x00010402, 0x00000000, /* DDR533 FSB800 */

View file

@ -38,7 +38,7 @@ static void sdram_read_spds(struct sysinfo *s)
int status = 0;
FOR_EACH_DIMM(i) {
if (s->spd_map[i] == 0) {
/* Non-existant SPD address */
/* Non-existent SPD address */
s->dimms[i].card_type = 0;
continue;
}

View file

@ -36,7 +36,7 @@ static void vx900_print_sata_errors(u32 flags)
printk(BIOS_DEBUG, "\tCOMWAKE %s\n",
(flags & (1 << 16)) ? "detected" : "not detected");
printk(BIOS_DEBUG, "\tExchange as determined by COMINIT %s\n",
(flags & (1 << 26)) ? "occured" : "not occured");
(flags & (1 << 26)) ? "occurred" : "not occurred");
printk(BIOS_DEBUG, "\tPort selector presence %s\n",
(flags & (1 << 27)) ? "detected" : "not detected");
/* Errors */