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src/drivers: Add required space before opening parenthesis '('

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Change-Id: I4d0087b2557862d04be54cf42f01b3223cb723ac
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16321
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-08-25 20:50:50 +02:00 • committed by Martin Roth
commit 2e4d80687d
8 changed files with 21 additions and 21 deletions
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2
src/drivers/intel/fsp1_0/fsp_util.c
View file

@ -303,7 +303,7 @@ static void find_fsp_hob_update_mrc(void *unused)
print_hob_type_structure(0x000, FspHobListPtr);
#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
if(save_mrc_data(FspHobListPtr))
if (save_mrc_data(FspHobListPtr))
update_mrc_cache(NULL);
else
printk(BIOS_DEBUG,"Not updating MRC data in flash.\n");

2
src/drivers/intel/fsp1_1/ramstage.c
View file

@ -143,7 +143,7 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
/* Mark graphics init done after SiliconInit if VBT was provided */
#if IS_ENABLED(CONFIG_GOP_SUPPORT)
/* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs
* to be #if'd out instead of using if(). */
* to be #if'd out instead of using if (). */
if (silicon_init_params.GraphicsConfigPtr)
gfx_set_init_done(1);
#endif

6
src/drivers/intel/gma/intel_dp.c
View file

@ -642,7 +642,7 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
(unsigned long)gtt_read(PCH_PP_STATUS),
(unsigned long)gtt_read(PCH_PP_CONTROL));
for(i = 0, status = gtt_read(PCH_PP_STATUS); ((status & mask) != value) && (i < 5000);
for (i = 0, status = gtt_read(PCH_PP_STATUS); ((status & mask) != value) && (i < 5000);
status = gtt_read(PCH_PP_STATUS)){
udelay(10);
}
@ -972,7 +972,7 @@ intel_dp_get_link_status(struct intel_dp *intel_dp,
DP_LINK_STATUS_SIZE);
printk(BIOS_SPEW, "%s:", __func__);
for(i = 0; i < /* !!sizeof(link_status) == 4*/
for (i = 0; i < /* !!sizeof(link_status) == 4*/
DP_LINK_STATUS_SIZE; i++)
printk(BIOS_SPEW, " %02x", link_status[i]);
printk(BIOS_SPEW, "\n");
@ -1308,7 +1308,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
gtt_write(DP_TP_CTL(port), temp);
for(i = 0; i < 10; i++){
for (i = 0; i < 10; i++){
u32 status;
status = gtt_read(DP_TP_STATUS(port));
if (status & DP_TP_STATUS_IDLE_DONE)