From 2e47bd50f2c48db4732a5c864272d066cdd77de0 Mon Sep 17 00:00:00 2001
From: lizheng <lizheng@huaqin.corp-partner.google.com>
Date: Thu, 17 Jul 2025 11:19:44 +0800
Subject: [PATCH] mb/google/trulo/var/pujjocento: Add 6W and 15W DPTF
 parameters

The DPTF parameters were defined by the thermal team.
Based on thermal table in 432114256 comment#1

BUG=b:432114256
TEST=emerge-nissa coreboot chromeos-bootimage
Signed-off-by: lizheng <lizheng@huaqin.corp-partner.google.com>

Change-Id: I969f93f384bb2a59f1300478794f48e30997736d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88463
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 .../google/brya/variants/pujjocento/overridetree.cb  | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index 517d210598..d84f1000ea 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -156,6 +156,18 @@ chip soc/intel/alderlake
 		},
 	}"
 
+	# Power limit config
+	register "power_limits_config[ADL_N_041_6W_CORE]" = "{
+		.tdp_pl1_override = 13,
+		.tdp_pl2_override = 25,
+		.tdp_pl4 = 78,
+	}"
+	register "power_limits_config[ADL_N_081_15W_CORE]" = "{
+		.tdp_pl1_override = 22,
+		.tdp_pl2_override = 35,
+		.tdp_pl4 = 83,
+	}"
+
 	device domain 0 on
 		device ref dtt on
 			chip drivers/intel/dptf