From 2e3e690023aeb1679509a008d34dbf2e3f44fe77 Mon Sep 17 00:00:00 2001 From: Hari L Date: Tue, 3 Mar 2026 15:31:53 +0530 Subject: [PATCH] soc/qualcomm/x1p42100: Support to load ADSP Lite firmware MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ADSP Lite firmware along with its corresponding DTB must be loaded from coreboot to allow the LPASS/ADSP subsystem to initialize correctly.ADSP lite firmware supports off-mode charging. This patch adds support to load the ADSP DTB and ADSP firmware images on the X1P42100 platform. The register programming details required for loading ADSP are derived from the HRD-X1P42100-S1 document. Reference: https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/ TEST=1. Create an image.serial.bin and ensure it boots on X1P42100. 2. Verified using ADSP load log from coreboot showing successful loading of ADSP DTB and ADSP firmware: 'SOC:LPASS/ADSP image loaded successfully' Logs: [INFO ]  Initializing devices... [DEBUG]  Root Device init [DEBUG]  Starting cbfs_boot_device [DEBUG]  FMAP: area FW_MAIN_A found @ c30000 (8904448 bytes) [INFO ]  CBFS: Found 'fallback/adsp_dtbs' @0x237200 size 0x10794 in mcache @0x8669d794 [DEBUG]  Starting cbfs_boot_device [INFO ]  CBFS: Found 'fallback/adsp_dtbs' @0x237200 size 0x10794 in mcache @0x8669d794 [DEBUG]  read SPI 0xe67258 0x10794: 3662 us, 18425 KB/s, 147.400 Mbps [INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not supported for secdata_kernel v0, return 0 [INFO ]  VB2:vb2_digest_init() 67476 bytes, hash algo 2, HW acceleration forbidden [DEBUG]  Loading segment from ROM address 0x9f800000 [DEBUG]    code (compression=0) [DEBUG]    New segment dstaddr 0x866c0000 memsize 0x1075c srcaddr 0x9f800038 filesize 0x1075c [DEBUG]  Loading Segment: addr: 0x866c0000 memsz: 0x000000000001075c filesz: 0x000000000001075c [DEBUG]  it's not compressed! [SPEW ]  [ 0x866c0000, 866d075c, 0x866d075c) <- 9f800038 [DEBUG]  Loading segment from ROM address 0x9f80001c [DEBUG]    Entry Point 0x866c0000 [SPEW ]  Loaded segments [DEBUG]  Starting cbfs_boot_device [INFO ]  CBFS: Found 'fallback/adsp_lite' @0xe7ac0 size 0x14f6aa in mcache @0x8669d73c [DEBUG]  read SPI 0xd17b18 0x14f6aa: 74126 us, 18534 KB/s, 148.272 Mbps [INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not supported for secdata_kernel v0, return 0 [INFO ]  VB2:vb2_digest_init() 1373866 bytes, hash algo 2, HW acceleration forbidden [DEBUG]  Loading segment from ROM address 0x9f800000 [DEBUG]    code (compression=1) [DEBUG]    New segment dstaddr 0x86b00000 memsize 0x5000 srcaddr 0x9f800268 filesize 0x2072 [DEBUG]  Loading Segment: addr: 0x86b00000 memsz: 0x0000000000005000 filesz: 0x0000000000002072 [DEBUG]  using LZMA [SPEW ]  [ 0x86b00000, 86b04620, 0x86b05000) <- 9f800268 [DEBUG]  Clearing Segment: addr: 0x0000000086b04620 memsz: 0x00000000000009e0 [DEBUG]  Loading segment from ROM address 0x9f80001c [DEBUG]    data (compression=1) [DEBUG]    New segment dstaddr 0x86b05000 memsize 0x240000 srcaddr 0x9f8022da filesize 0x6cf [DEBUG]  Loading Segment: addr: 0x86b05000 memsz: 0x0000000000240000 filesz: 0x00000000000006cf [DEBUG]  using LZMA [SPEW ]  [ 0x86b05000, 86b14ffc, 0x86d45000) <- 9f8022da [DEBUG]  Clearing Segment: addr: 0x0000000086b14ffc memsz: 0x0000000000230004 [DEBUG]  Loading segment from ROM address 0x9f800038 [DEBUG]    code (compression=1) [DEBUG]    New segment dstaddr 0x86d45000 memsize 0x12000 srcaddr 0x9f8029a9 filesize 0xa2d6 [DEBUG]  Loading Segment: addr: 0x86d45000 memsz: 0x0000000000012000 filesz: 0x000000000000a2d6 [DEBUG]  using LZMA [SPEW ]  [ 0x86d45000, 86d567dc, 0x86d57000) <- 9f8029a9 [DEBUG]  Clearing Segment: addr: 0x0000000086d567dc memsz: 0x0000000000000824 [DEBUG]  Loading segment from ROM address 0x9f800054 [DEBUG]    code (compression=1) [DEBUG]    New segment dstaddr 0x86d57000 memsize 0x7000 srcaddr 0x9f80cc7f filesize 0x3c6c [DEBUG]  Loading Segment: addr: 0x86d57000 memsz: 0x0000000000007000 filesz: 0x0000000000003c6c [DEBUG]  using LZMA [SPEW ]  [ 0x86d57000, 86d5da34, 0x86d5e000) <- 9f80cc7f [DEBUG]  Clearing Segment: addr: 0x0000000086d5da34 memsz: 0x00000000000005cc [DEBUG]  Loading segment from ROM address 0x9f800070 [DEBUG]    code (compression=1) [DEBUG]    New segment dstaddr 0x86d5e000 memsize 0x8000 srcaddr 0x9f8108eb filesize 0x538 [DEBUG]  Loading Segment: addr: 0x86d5e000 memsz: 0x0000000000008000 filesz: 0x0000000000000538 [DEBUG]  using LZMA [SPEW ]  [ 0x86d5e000, 86d65850, 0x86d66000) <- 9f8108eb [DEBUG]  Clearing Segment: addr: 0x0000000086d65850 memsz: 0x00000000000007b0 [DEBUG]  Loading segment from ROM address 0x9f80008c [DEBUG]    code (compression=1) [DEBUG]    New segment dstaddr 0x86d70000 memsize 0x1000 srcaddr 0x9f810e23 filesize 0xc4 [DEBUG]  Loading Segment: addr: 0x86d70000 memsz: 0x0000000000001000 filesz: 0x00000000000000c4 [DEBUG]  using LZMA [SPEW ]  [ 0x86d70000, 86d700f0, 0x86d71000) <- 9f810e23 [DEBUG]  Clearing Segment: addr: 0x0000000086d700f0 memsz: 0x0000000000000f10 [DEBUG]  Loading segment from ROM address 0x9f8000a8 [DEBUG]    data (compression=1) [DEBUG]    New segment dstaddr 0x86d71000 memsize 0x3000 srcaddr 0x9f810ee7 filesize 0x4b1 [DEBUG]  Loading Segment: addr: 0x86d71000 memsz: 0x0000000000003000 filesz: 0x00000000000004b1 [DEBUG]  using LZMA [SPEW ]  [ 0x86d71000, 86d7384c, 0x86d74000) <- 9f810ee7 [DEBUG]  Clearing Segment: addr: 0x0000000086d7384c memsz: 0x00000000000007b4 [DEBUG]  Loading segment from ROM address 0x9f8000c4 [DEBUG]    code (compression=1) [DEBUG]    New segment dstaddr 0x86d74000 memsize 0x192000 srcaddr 0x9f811398 filesize 0xafc41 [DEBUG]  Loading Segment: addr: 0x86d74000 memsz: 0x0000000000192000 filesz: 0x00000000000afc41 [DEBUG]  using LZMA [SPEW ]  [ 0x86d74000, 86f054a4, 0x86f06000) <- 9f811398 [DEBUG]  Clearing Segment: addr: 0x0000000086f054a4 memsz: 0x0000000000000b5c [DEBUG]  Loading segment from ROM address 0x9f8000e0 [DEBUG]    data (compression=1) [DEBUG]    New segment dstaddr 0x86f06000 memsize 0x375000 srcaddr 0x9f8c0fd9 filesize 0xb722 [DEBUG]  Loading Segment: addr: 0x86f06000 memsz: 0x0000000000375000 filesz: 0x000000000000b722 [DEBUG]  using LZMA [SPEW ]  [ 0x86f06000, 86f7392c, 0x8727b000) <- 9f8c0fd9 [DEBUG]  Clearing Segment: addr: 0x0000000086f7392c memsz: 0x00000000003076d4 [DEBUG]  Loading segment from ROM address 0x9f8000fc [DEBUG]    data (compression=1) [DEBUG]    New segment dstaddr 0x8727b000 memsize 0x1000 srcaddr 0x9f8cc6fb filesize 0x1d [DEBUG]  Loading Segment: addr: 0x8727b000 memsz: 0x0000000000001000 filesz: 0x000000000000001d [DEBUG]  using LZMA [SPEW ]  [ 0x8727b000, 8727b2a0, 0x8727c000) <- 9f8cc6fb [DEBUG]  Clearing Segment: addr: 0x000000008727b2a0 memsz: 0x0000000000000d60 [DEBUG]  Loading segment from ROM address 0x9f800118 [DEBUG]    data (compression=1) [DEBUG]    New segment dstaddr 0x8727c000 memsize 0x15000 srcaddr 0x9f8cc718 filesize 0x3d04 [DEBUG]  Loading Segment: addr: 0x8727c000 memsz: 0x0000000000015000 filesz: 0x0000000000003d04 [DEBUG]  using LZMA [SPEW ]  [ 0x8727c000, 8729023c, 0x87291000) <- 9f8cc718 [DEBUG]  Clearing Segment: addr: 0x000000008729023c memsz: 0x0000000000000dc4 [DEBUG]  Loading segment from ROM address 0x9f800134 [DEBUG]    data (compression=1) [DEBUG]    New segment dstaddr 0x87291000 memsize 0x1000 srcaddr 0x9f8d041c filesize 0x16c [DEBUG]  Loading Segment: addr: 0x87291000 memsz: 0x0000000000001000 filesz: 0x000000000000016c [DEBUG]  using LZMA [SPEW ]  [ 0x87291000, 87291587, 0x87292000) <- 9f8d041c [DEBUG]  Clearing Segment: addr: 0x0000000087291587 memsz: 0x0000000000000a79 [DEBUG]  Loading segment from ROM address 0x9f800150 [DEBUG]    data (compression=1) [DEBUG]    New segment dstaddr 0x87292000 memsize 0x24600 srcaddr 0x9f8d0588 filesize 0x52c [DEBUG]  Loading Segment: addr: 0x87292000 memsz: 0x0000000000024600 filesz: 0x000000000000052c [DEBUG]  using LZMA [SPEW ]  [ 0x87292000, 872b6600, 0x872b6600) <- 9f8d0588 [DEBUG]  Loading segment from ROM address 0x9f80016c [DEBUG]    data (compression=1) [DEBUG]    New segment dstaddr 0x872b6600 memsize 0x2a00 srcaddr 0x9f8d0ab4 filesize 0xef0 [DEBUG]  Loading Segment: addr: 0x872b6600 memsz: 0x0000000000002a00 filesz: 0x0000000000000ef0 [DEBUG]  using LZMA [SPEW ]  [ 0x872b6600, 872b8de9, 0x872b9000) <- 9f8d0ab4 [DEBUG]  Clearing Segment: addr: 0x00000000872b8de9 memsz: 0x0000000000000217 [DEBUG]  Loading segment from ROM address 0x9f800188 [DEBUG]    data (compression=1) [DEBUG]    New segment dstaddr 0x872b9000 memsize 0x6c srcaddr 0x9f8d19a4 filesize 0x4b [DEBUG]  Loading Segment: addr: 0x872b9000 memsz: 0x000000000000006c filesz: 0x000000000000004b [DEBUG]  using LZMA [SPEW ]  [ 0x872b9000, 872b906c, 0x872b906c) <- 9f8d19a4 [DEBUG]  Loading segment from ROM address 0x9f8001a4 [DEBUG]    code (compression=1) [DEBUG]    New segment dstaddr 0x872b906c memsize 0x1cf94 srcaddr 0x9f8d19ef filesize 0xffcc [DEBUG]  Loading Segment: addr: 0x872b906c memsz: 0x000000000001cf94 filesz: 0x000000000000ffcc [DEBUG]  using LZMA [SPEW ]  [ 0x872b906c, 872d5368, 0x872d6000) <- 9f8d19ef [DEBUG]  Clearing Segment: addr: 0x00000000872d5368 memsz: 0x0000000000000c98 [DEBUG]  Loading segment from ROM address 0x9f8001c0 [DEBUG]    code (compression=1) [DEBUG]    New segment dstaddr 0x872e0000 memsize 0x1e0000 srcaddr 0x9f8e19bb filesize 0x62e09 [DEBUG]  Loading Segment: addr: 0x872e0000 memsz: 0x00000000001e0000 filesz: 0x0000000000062e09 [DEBUG]  using LZMA [SPEW ]  [ 0x872e0000, 874bf3c4, 0x874c0000) <- 9f8e19bb [DEBUG]  Clearing Segment: addr: 0x00000000874bf3c4 memsz: 0x0000000000000c3c [DEBUG]  Loading segment from ROM address 0x9f8001dc [DEBUG]    data (compression=1) [DEBUG]    New segment dstaddr 0x874c0000 memsize 0xef000 srcaddr 0x9f9447c4 filesize 0xd8f [DEBUG]  Loading Segment: addr: 0x874c0000 memsz: 0x00000000000ef000 filesz: 0x0000000000000d8f [DEBUG]  using LZMA [SPEW ]  [ 0x874c0000, 874c4130, 0x875af000) <- 9f9447c4 [DEBUG]  Clearing Segment: addr: 0x00000000874c4130 memsz: 0x00000000000eaed0 [DEBUG]  Loading segment from ROM address 0x9f8001f8 [DEBUG]    data (compression=1) [DEBUG]    New segment dstaddr 0x875af000 memsize 0x1000 srcaddr 0x9f945553 filesize 0x3a [DEBUG]  Loading Segment: addr: 0x875af000 memsz: 0x0000000000001000 filesz: 0x000000000000003a [DEBUG]  using LZMA [SPEW ]  [ 0x875af000, 875af078, 0x875b0000) <- 9f945553 [DEBUG]  Clearing Segment: addr: 0x00000000875af078 memsz: 0x0000000000000f88 [DEBUG]  Loading segment from ROM address 0x9f800214 [DEBUG]    data (compression=1) [DEBUG]    New segment dstaddr 0x875b0000 memsize 0x4f000 srcaddr 0x9f94558d filesize 0xa11d [DEBUG]  Loading Segment: addr: 0x875b0000 memsz: 0x000000000004f000 filesz: 0x000000000000a11d [DEBUG]  using LZMA [SPEW ]  [ 0x875b0000, 875fefd4, 0x875ff000) <- 9f94558d [DEBUG]  Clearing Segment: addr: 0x00000000875fefd4 memsz: 0x000000000000002c [DEBUG]  Loading segment from ROM address 0x9f800230 [DEBUG]    BSS 0x875ff000 (1052672 byte) [DEBUG]  Loading Segment: addr: 0x875ff000 memsz: 0x0000000000101000 filesz: 0x0000000000000000 [DEBUG]  it's not compressed! [SPEW ]  [ 0x875ff000, 875ff000, 0x87700000) <- 9f94f6aa [DEBUG]  Clearing Segment: addr: 0x00000000875ff000 memsz: 0x0000000000101000 [DEBUG]  Loading segment from ROM address 0x9f80024c [DEBUG]    Entry Point 0x86b00000 [SPEW ]  Loaded segments [INFO] SOC: LPASS/ADSP image loaded successfully Change-Id: I04ebd71bc06c971a39f0d4ae9fe299a64dfaaff8 Signed-off-by: Hari L Reviewed-on: https://review.coreboot.org/c/coreboot/+/91520 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Jayvik Desai Reviewed-by: Kapil Porwal --- src/soc/qualcomm/x1p42100/Makefile.mk | 18 +++ src/soc/qualcomm/x1p42100/adsp_load_reset.c | 119 ++++++++++++++++++ .../x1p42100/include/soc/addressmap.h | 2 + src/soc/qualcomm/x1p42100/include/soc/adsp.h | 40 ++++++ .../x1p42100/include/soc/platform_info.h | 53 ++++++++ 5 files changed, 232 insertions(+) create mode 100644 src/soc/qualcomm/x1p42100/adsp_load_reset.c create mode 100644 src/soc/qualcomm/x1p42100/include/soc/adsp.h create mode 100644 src/soc/qualcomm/x1p42100/include/soc/platform_info.h diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk index dbb125aff9..cfb8410e60 100644 --- a/src/soc/qualcomm/x1p42100/Makefile.mk +++ b/src/soc/qualcomm/x1p42100/Makefile.mk @@ -56,6 +56,7 @@ ramstage-$(CONFIG_PCI) += ../common/pcie_common.c ramstage-y += ../common/spmi.c ramstage-$(CONFIG_PCI) += pcie.c ramstage-y += cpucp_load_reset.c +ramstage-y += adsp_load_reset.c ramstage-y += ../common/cmd_db.c ramstage-y += ../common/rpmh.c ../common/rpmh_bcm.c ../common/rpmh_regulator.c ../common/rpmh_rsc.c ramstage-y += rpmh_rsc_init.c @@ -249,6 +250,23 @@ $(CPUCP_DTBS_CBFS)-type := payload $(CPUCP_DTBS_CBFS)-compression := $(CBFS_COMPRESS_FLAG) cbfs-files-y += $(CPUCP_DTBS_CBFS) +################################################################################ +# ADSP (Audio DSP) Lite Firmware for Off-mode charging +################################################################################ +ADSP_LITE_FILE := $(X1P42100_BLOB)/adsp/adsp.mbn +ADSP_LITE_CBFS := $(CONFIG_CBFS_PREFIX)/adsp_lite +$(ADSP_LITE_CBFS)-file := $(ADSP_LITE_FILE) +$(ADSP_LITE_CBFS)-type := payload +$(ADSP_LITE_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(ADSP_LITE_CBFS) + +################################################################################ +ADSP_DTBS_FILE := $(X1P42100_BLOB)/adsp/adsp_dtbs.elf +ADSP_DTBS_CBFS := $(CONFIG_CBFS_PREFIX)/adsp_dtbs +$(ADSP_DTBS_CBFS)-file := $(ADSP_DTBS_FILE) +$(ADSP_DTBS_CBFS)-type := payload +cbfs-files-y += $(ADSP_DTBS_CBFS) + ################################################################################ SHRM_FILE := $(X1P42100_BLOB)/$(BLOB_VARIANT)/shrm/shrm.elf SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm diff --git a/src/soc/qualcomm/x1p42100/adsp_load_reset.c b/src/soc/qualcomm/x1p42100/adsp_load_reset.c new file mode 100644 index 0000000000..03433e8e6f --- /dev/null +++ b/src/soc/qualcomm/x1p42100/adsp_load_reset.c @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +/** + * lpass_program_boot_addr() - Program ADSP boot address override + * @addr: ADSP firmware entry address + * + * Program EVB address/select so Q6 boots from @addr. + */ +static void lpass_program_boot_addr(uintptr_t addr) +{ + write32(&lpass_efuse_q6ss->evb_addr, (addr>>4)); + write32(&lpass_efuse_q6ss->evb_sel, EVB_ENABLE); + dsb(); +} + +/** + * lpass_dtb_bring_up() - Configure ADSP Device Tree Boot parameters + * @dtb_entry_addr: Physical address where Device Tree image is loaded + * @dtb_size: Size of Device Tree image in bytes + * + * Configure the QDSP6SS boot parameter registers with: + * - Device Tree blob location and size + * - Chip identification (family and ID) + * - Chip version information + * - Platform type and version + * + * Boot Parameter Register Layout: + * BOOT_PARAMS[0]: DTB address (lower 32 bits) + * BOOT_PARAMS[1]: DTB address (upper 32 bits) + * BOOT_PARAMS[2]: Chip family (bits 31:16) | Chip ID (bits 15:0) + * BOOT_PARAMS[3]: Chip version - Major (bits 15:8) | Minor (bits 7:0) + * BOOT_PARAMS[4]: Platform type (bits 31:24) | Subtype (bits 23:16) | + * Version major (bits 15:8) | Version minor (bits 7:0) not programmed + * BOOT_PARAMS[5]: DTB size + * + * Return: CB_SUCCESS on success, CB_ERR on failure + */ +static enum cb_err lpass_dtb_bring_up(uintptr_t dtb_entry_addr, size_t dtb_size) +{ + uint32_t chip_family, chip_id; + uint32_t chip_major, chip_minor; + uint32_t boot_params2, boot_params3; + + write32(&lpass_qdsp6ss->boot_params[0], (uint32_t)(dtb_entry_addr & 0xFFFFFFFF)); + write32(&lpass_qdsp6ss->boot_params[1], (uint32_t)(dtb_entry_addr >> 32)); + + /* x1p42100 uses fixed SoC boot args; do not depend on SMEM init ordering. */ + + chip_family = CHIPINFO_FAMILY & CHIP_FAMILY_MASK; + chip_id = CHIPINFO_ID_SCP & CHIP_ID_MASK; + boot_params2 = (chip_family << CHIP_FAMILY_SHIFT) | chip_id; + + chip_major = CHIPINFO_CHIP_VERSION_MAJOR; + chip_minor = CHIPINFO_CHIP_VERSION_MINOR; + boot_params3 = ((chip_major & CHIP_VERSION_MASK) << CHIP_VERSION_MAJOR_SHIFT) | + (chip_minor & CHIP_VERSION_MASK); + + write32(&lpass_qdsp6ss->boot_params[2], boot_params2); + write32(&lpass_qdsp6ss->boot_params[3], boot_params3); + write32(&lpass_qdsp6ss->boot_params[5], (uint32_t)dtb_size); + dsb(); + + return CB_SUCCESS; +} + +/** + * adsp_fw_load() - Main entry point for ADSP firmware loading + * + * Orchestrate the complete ADSP firmware loading sequence: + * 1. Load ADSP Device Tree Blob from CBFS + * 2. Configure QDSP6SS boot parameters with DTB location and platform info + * 3. Load ADSP firmware from CBFS + * 4. Program ADSP boot address via EFUSE EVB registers + */ +void adsp_fw_load(void) +{ + struct prog adsp_dtbs_prog = PROG_INIT(PROG_PAYLOAD, ADSP_CBFS_DTBS); + struct prog adsp_fw_prog = PROG_INIT(PROG_PAYLOAD, ADSP_CBFS_FIRMWARE); + uintptr_t dtb_entry_addr; + uintptr_t fw_entry_addr; + size_t dtb_size; + + dtb_size = cbfs_get_size(ADSP_CBFS_DTBS); + if (dtb_size == 0) { + printk(BIOS_ERR, "ADSP: Failed to get DTBS size from CBFS\n"); + return; + } + + if (!selfload(&adsp_dtbs_prog)) { + printk(BIOS_ERR, "ADSP: DTBS load failed\n"); + return; + } + + dtb_entry_addr = (uintptr_t)prog_entry(&adsp_dtbs_prog); + + if (lpass_dtb_bring_up(dtb_entry_addr, dtb_size) != CB_SUCCESS) { + printk(BIOS_ERR, "ADSP: DTB bring up failed\n"); + return; + } + + if (!selfload(&adsp_fw_prog)) { + printk(BIOS_ERR, "ADSP: Firmware load failed\n"); + return; + } + + fw_entry_addr = (uintptr_t)prog_entry(&adsp_fw_prog); + + lpass_program_boot_addr(fw_entry_addr); + + printk(BIOS_INFO, "SOC: LPASS/ADSP image loaded successfully\n"); +} diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h index dc45a668d6..6cb4b231e2 100644 --- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h +++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h @@ -24,6 +24,8 @@ #define LPASS_AON_CC_BASE (LPASS_BASE + 0x00E08000) #define LPASS_AON_CC_PLL_CM_BASE (LPASS_BASE + 0x00E01000) #define LPASS_CORE_GDSC_REG_BASE (LPASS_BASE + 0x01E00000) +#define LPASS_QDSP6SS_PUB_BASE (LPASS_BASE + 0x00800000) +#define LPASS_EFUSE_Q6SS_BASE (LPASS_BASE + 0x0125B000) #define RPMH_BASE 0x17520000 #define CMD_DB_BASE_ADDR 0x81c60000 diff --git a/src/soc/qualcomm/x1p42100/include/soc/adsp.h b/src/soc/qualcomm/x1p42100/include/soc/adsp.h new file mode 100644 index 0000000000..5e156f210b --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/adsp.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_QUALCOMM_X1P42100_ADSP_H__ +#define __SOC_QUALCOMM_X1P42100_ADSP_H__ + +#include +#include +#include +#include + +/* ADSP CBFS firmware paths */ +#define ADSP_CBFS_DTBS CONFIG_CBFS_PREFIX "/adsp_dtbs" +#define ADSP_CBFS_FIRMWARE CONFIG_CBFS_PREFIX "/adsp_lite" + +/* LPASS QDSP6SS Register Structure */ +struct x1p42100_lpass_qdsp6ss { + u8 _res0[0x10]; + u32 rst_evb; + u8 _res1[0x60 - 0x14]; + u32 boot_params[6]; +}; + +check_member(x1p42100_lpass_qdsp6ss, rst_evb, 0x10); +check_member(x1p42100_lpass_qdsp6ss, boot_params, 0x60); + +/* LPASS EFUSE Q6SS Register Structure */ +struct x1p42100_lpass_efuse_q6ss { + u32 evb_sel; + u32 evb_addr; +}; + +check_member(x1p42100_lpass_efuse_q6ss, evb_sel, 0x0); +check_member(x1p42100_lpass_efuse_q6ss, evb_addr, 0x4); + +static struct x1p42100_lpass_qdsp6ss *const lpass_qdsp6ss = (void *)LPASS_QDSP6SS_PUB_BASE; +static struct x1p42100_lpass_efuse_q6ss *const lpass_efuse_q6ss = (void *)LPASS_EFUSE_Q6SS_BASE; + +void adsp_fw_load(void); + +#endif /* __SOC_QUALCOMM_X1P42100_ADSP_H__ */ diff --git a/src/soc/qualcomm/x1p42100/include/soc/platform_info.h b/src/soc/qualcomm/x1p42100/include/soc/platform_info.h new file mode 100644 index 0000000000..bf27c7cb92 --- /dev/null +++ b/src/soc/qualcomm/x1p42100/include/soc/platform_info.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __SOC_QUALCOMM_X1P42100_PLATFORM_INFO_H__ +#define __SOC_QUALCOMM_X1P42100_PLATFORM_INFO_H__ + +/* ADSP BOOT_PARAMS helpers */ + +/* BOOT_PARAMS bitfield definitions */ +#define CHIP_FAMILY_MASK 0xFFFF +#define CHIP_FAMILY_SHIFT 16 +#define CHIP_ID_MASK 0xFFFF +#define CHIP_VERSION_MAJOR_SHIFT 8 +#define CHIP_VERSION_MASK 0xFF +#define PLATFORM_FIELD_MASK 0xFF +#define PLATFORM_SUBTYPE_SHIFT 16 +#define PLATFORM_TYPE_SHIFT 24 +#define PLATFORM_VERSION_MAJOR_SHIFT 8 + +#define EVB_ENABLE 1 + +/* + * ADSP BOOT_PARAMS chipinfo identifiers. + * + * Keep values as macros (no literals in packer code) to match SMEM chipinfo: + * - CHIPINFO_FAMILY_*: eChipInfoFamily + * - CHIPINFO_ID_SCP_*: eChipInfoId (SCP) + */ +#if CONFIG(SOC_QUALCOMM_HAMOA) +/* Hamoa (SC8380XP) identifiers used by ADSP BOOT_PARAMS on x1p42100 platforms. */ +#define CHIPINFO_FAMILY 0x0088 +#define CHIPINFO_ID_SCP 0x022B + +/* Hamoa chip version used for BOOT_PARAMS[3] packing. */ +#define CHIPINFO_CHIP_VERSION 0x00020000 /* nChipVersion (SMEM) */ +#define CHIPINFO_CHIP_VERSION_MAJOR 0x02 +#define CHIPINFO_CHIP_VERSION_MINOR 0x00 +#else +/* Purwa Compute (SC8340XP / X1P4x100) */ +#define CHIPINFO_FAMILY 0x009A +#define CHIPINFO_ID_SCP 0x027B + +#define CHIPINFO_CHIP_VERSION 0x00020000 /* nChipVersion (SMEM) */ +#define CHIPINFO_CHIP_VERSION_MAJOR 0x02 +#define CHIPINFO_CHIP_VERSION_MINOR 0x00 +#endif + +/* x1p42100 platform info used for BOOT_PARAMS[4] packing. */ +#define PLATFORMINFO_TYPE 0x28 /* ePlatformType */ +#define PLATFORMINFO_SUBTYPE 0x00 /* nPlatformSubtype */ +#define PLATFORMINFO_VERSION 0x00010000 /* nPlatformVersion */ +#define PLATFORMINFO_VERSION_MAJOR 0x01 +#define PLATFORMINFO_VERSION_MINOR 0x00 + +#endif /* __SOC_QUALCOMM_X1P42100_PLATFORM_INFO_H__ */