soc/intel/pantherlake: Add asynchronous CBFS file loading support

This commit introduces support for asynchronous coreboot File
System (CBFS) file loading from SPINOR, specifically targeting the
fsps.bin file, in the Intel Panther Lake (PTL) System on a Chip (SoC)
platform. The primary motivation for this change is to improve boot time
performance by utilizing SPI Direct Memory Access (DMA) to preload files
while the Central Processing Unit (CPU) continues executing other tasks.

This feature uses cooperative multithreading. Because the scheduling is
cooperative, the boot process stays mostly predictable, which minimizes
debugging difficulties while still enhancing boot performance.

The preload operations are strategically modified according to the
chipset lockdown settings. This guarantees that payload preloading is
finalized prior to SPI DMA locking when the chipset lockdown is managed
by FSP or otherwise maximizes the pre-loading feature.

Note: As there is no UPD to control the Fast DMI DMA interface lockdown,
a special FSP binary, built without the Fast SPI DMA driver
(PcdSpiDmaEnable), is required when chipset lockdown setting is set to
CHIPSET_LOCKDOWN_COREBOOT.

TEST=On a Fatcat device, with CHIPSET_LOCKDOWN_COREBOOT, the boot time
     has improved by around 17-18 ms.

Change-Id: I4106058d382b99eac5f988c134cc02f024f7d473
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88300
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/pantherlake/Kconfig

@@ -6,6 +6,8 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select ARCH_X86
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
+	select CBFS_PRELOAD
+	select COOP_MULTITASKING
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_VOLTAGE
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
@@ -16,6 +18,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select POSTPONE_SPI_ACCESS
 	select DISPLAY_FSP_VERSION_INFO_2
 	select DRIVERS_USB_ACPI
+	select FAST_SPI_DMA
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
 	select FSP_COMPRESS_FSP_S_LZ4
 	select FSP_M_XIP
@@ -460,4 +463,13 @@ config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
 	bool
 	default n
 
+# Increase the CBFS cache size to accommodate FSP-S binary pre-loading
+# process.
+config RAMSTAGE_CBFS_CACHE_SIZE
+	default 0xd0000
+
+# Fast SPI DMA operations require 1 KiB-aligned memory buffers.
+config CBFS_CACHE_ALIGN
+	default 1024
+
 endif

src/soc/intel/pantherlake/Makefile.mk

@@ -26,6 +26,7 @@ romstage-y += pcie_rp.c
 romstage-y += reset.c
 
 ramstage-y += acpi.c
+ramstage-y += cbfs_preload.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
 ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c

src/soc/intel/pantherlake/cbfs_preload.c

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <cbfs.h>
+#include <fsp/api.h>
+#include <intelblocks/cfg.h>
+#include <program_loading.h>
+
+static void preload_pre_fsps(void *unused)
+{
+	preload_fsps();
+
+	struct soc_intel_common_config *config = chip_get_common_soc_structure();
+	/* If chipset lockdown is handled by FSP, CBFS pre-loading must be completed
+	   before FSP-S finishes. In this case, it yields better results to preload the
+	   payload before lockdown.*/
+	if (config->chipset_lockdown == CHIPSET_LOCKDOWN_FSP)
+		payload_preload();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, preload_pre_fsps, NULL);
+
+static void preload_post_fsps(void *unused)
+{
+	struct soc_intel_common_config *config = chip_get_common_soc_structure();
+	/* If the chipset lockdown is handled by FSP, SPI DMA is locked, and we cannot
+	   preload any other CBFS files. */
+	if (config->chipset_lockdown == CHIPSET_LOCKDOWN_FSP)
+		return;
+
+	cbfs_preload(CONFIG_CBFS_PREFIX "/dsdt.aml");
+	payload_preload();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, preload_post_fsps, NULL);

src/soc/intel/pantherlake/fsp_params.c

@@ -2,6 +2,7 @@
 
 #include <boot/coreboot_tables.h>
 #include <bootmode.h>
+#include <cbfs.h>
 #include <cpu/intel/microcode.h>
 #include <fsp/api.h>
 #include <fsp/debug.h>
@@ -832,6 +833,11 @@ void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index)
 			const struct soc_intel_pantherlake_config *config = config_of_soc();
 			tcss_configure(config->typec_aux_bias_pads);
 		}
+
+		/* Allow CBFS preload transfers to complete before FSP-S locks SPI DMA. */
+		struct soc_intel_common_config *config = chip_get_common_soc_structure();
+		if (config->chipset_lockdown == CHIPSET_LOCKDOWN_FSP)
+			cbfs_preload_wait_for_all();
 		break;
 	default:
 		break;