Add stage1 support for vt8237[RS] to v3.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@928 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Corey Osgood
parent
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commit
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3 changed files with 433 additions and 0 deletions
25
southbridge/via/vt8237/Makefile
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25
southbridge/via/vt8237/Makefile
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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ifeq ($(CONFIG_SOUTHBRIDGE_VIA_VT8237),y)
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STAGE2_CHIPSET_SRC +=
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endif
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318
southbridge/via/vt8237/stage1.c
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318
southbridge/via/vt8237/stage1.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 Corey Osgood <corey.osgood@gmail.com>
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <io.h>
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#include <device/pci_ids.h>
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#include <spd.h>
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#include "vt8237.h"
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/* TODO List:
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* * Merge the rest of the functions from v2, except smbus_fixup which doesn't
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* seem to be necessary any more (?)
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* * Clean up vt8237_early_network_init.
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* Comments in code indicate that it's broken?
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* * Figure out if the smbus actually needs to be reset after every transaction.
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*/
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/**
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* Print an error, should it occur. If no error, just exit.
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*
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* @param host_status The data returned on the host status register after
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* a transaction is processed.
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* @param loops The number of times a transaction was attempted.
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*/
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static void smbus_print_error(u8 host_status, int loops)
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{
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/* Check if there actually was an error. */
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if ((host_status == 0x00 || host_status == 0x40 ||
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host_status == 0x42) && (loops < SMBUS_TIMEOUT))
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{
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printk(BIOS_SPEW, "SMBus Ready/Completed Successfully\n");
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return;
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}
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if (loops >= SMBUS_TIMEOUT)
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printk(BIOS_ERR, "SMBus Timed out\n");
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if (host_status & (1 << 4))
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printk(BIOS_ERR, "Interrupt/SMI# was Failed Bus Transaction\n");
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if (host_status & (1 << 3))
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printk(BIOS_ERR, "Bus error\n");
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if (host_status & (1 << 2))
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printk(BIOS_ERR, "Device error\n");
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if (host_status & (1 << 1))
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printk(BIOS_SPEW, "Interrupt/SMI# completed successfully\n");
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if (host_status & (1 << 0))
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printk(BIOS_ERR, "Host busy\n");
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}
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/**
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* Reset and take ownership of the SMBus.
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*/
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static void smbus_reset(u16 smbus_io_base)
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{
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outb(HOST_RESET, smbus_io_base + SMBHSTSTAT);
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/* Datasheet says we have to read it to take ownership of SMBus. */
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smbus_print_error(inb(smbus_io_base + SMBHSTSTAT), 0);
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}
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/**
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* Wait for the SMBus to become ready to process the next transaction.
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*/
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static void smbus_wait_until_ready(u16 smbus_io_base)
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{
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int loops;
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printk(BIOS_SPEW, "Waiting until SMBus ready\n");
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loops = 0;
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while ((inb(smbus_io_base + SMBHSTSTAT) & 1) == 1 && loops <= SMBUS_TIMEOUT)
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++loops;
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smbus_print_error(inb(smbus_io_base + SMBHSTSTAT), loops);
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}
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/**
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* Read a byte from the SMBus.
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*
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* @param dimm The address location of the DIMM on the SMBus.
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* @param offset The offset the data is located at.
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*/
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u8 smbus_read_byte(u16 dimm, u8 offset, u16 smbus_io_base)
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{
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u8 val;
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printk(BIOS_SPEW, "SMBus Read from DIMM %d at address 0x%x\n",
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(int)dimm, offset);
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smbus_reset(smbus_io_base);
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/* Clear host data port. */
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outb(0x00, smbus_io_base + SMBHSTDAT0);
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/* Doesn't seem to be necessary...*/
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/* udelay(1); */
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smbus_wait_until_ready(smbus_io_base);
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/* With this, addresses are 0x50, 0x51, etc. Without it,
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* addresses would be 0xa1, 0xa3, etc */
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dimm = (dimm << 1) | 1;
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outb(dimm, smbus_io_base + SMBXMITADD);
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outb(offset, smbus_io_base + SMBHSTCMD);
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/* Start transaction, byte data read. */
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outb(0x48, smbus_io_base + SMBHSTCTL);
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/* udelay(1); */
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smbus_wait_until_ready(smbus_io_base);
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val = inb(smbus_io_base + SMBHSTDAT0);
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printk(BIOS_SPEW, "Read: 0x%x\n", val);
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/* TODO: Is this necessary? */
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smbus_reset(smbus_io_base);
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return val;
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}
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/**
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* Enable the smbus on vt8237-based systems
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*
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* @param smbus_io_base: The SMBus I/O base, usually 0x400
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*/
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void enable_smbus(u16 smbus_io_base)
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{
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u32 dev;
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/* Power management controller */
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pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC,
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&dev);
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if (!dev) {
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/* Power management controller */
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pci_conf1_find_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_VT8237S_LPC, &dev);
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if (!dev)
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{
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printk(BIOS_ERR, "Power management controller not "
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"found! Using hardcoded default.\n");
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dev = PCI_BDF(0, 17, 0);
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} else {
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printk(BIOS_DEBUG, "VT8237S Power management "
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"controller found at 0x%x\n", dev);
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}
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} else {
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printk(BIOS_DEBUG, "VT8237R Power management controller found "
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"at 0x%x\n", dev);
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}
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/* 7 = SMBus Clock from RTC 32.768KHz
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* 5 = Internal PLL reset from susp
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*/
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pci_conf1_write_config8(dev, VT8237R_POWER_WELL, 0xa0);
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/* Enable SMBus. */
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pci_conf1_write_config16(dev, VT8237R_SMBUS_IO_BASE_REG,
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smbus_io_base | 0x1);
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/* SMBus Host Configuration, enable. */
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pci_conf1_write_config8(dev, VT8237R_SMBUS_HOST_CONF, 0x01);
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/* Make it work for I/O. */
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pci_conf1_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
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/* reset smbus */
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smbus_reset(smbus_io_base);
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/* Reset the internal pointer. */
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inb(smbus_io_base + SMBHSTCTL);
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}
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/* TODO:
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* Magic numbers -> #defines
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* fix?
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* clean up
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*/
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/* offset 0x58
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* 31:20 reserved
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* 19:16 4 bit position in shadow EEPROM
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* 15:0 data to write
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*
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* offset 0x5c
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* 31:28 reserved
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* 27 ERDBG - enable read from 0x5c
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* 26 reserved
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* 25 SEELD
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* 24 SEEPR - write 1 when done updating, wait until SEELD is set to 1, sticky
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* cleared by reset, if it is 1 writing is disabled
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* 19:16 4 bit position in shadow EEPROM
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* 15:0 data from shadow EEPROM
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*
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* after PCIRESET SEELD and SEEPR must be 1 and 1
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*/
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/* 1 = needs PCI reset, 0 don't reset, network initialized */
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/* fixme maybe close the debug register after use? */
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#define LAN_TIMEOUT 0x7FFFFFFF
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int vt8237_early_network_init(struct vt8237_network_rom *rom) {
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struct vt8237_network_rom n;
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int loops = 0;
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u32 dev;
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u32 tmp;
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u8 status;
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u16 *rom_write;
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unsigned int checksum;
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int i;
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/* Network adapter */
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pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237_LAN,
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&dev);
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if (!dev) {
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printk(BIOS_ERR, "Network is disabled, please enable\n");
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return 0;
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}
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tmp = pci_conf1_read_config32(dev, 0x5c);
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/* enable ERDBG */
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tmp |= 0x08000000;
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pci_conf1_write_config32(dev, 0x5c, tmp);
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status = ((pci_conf1_read_config32(dev, 0x5c) >> 24) & 0x3);
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if (status == 3) {
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/* network controller OK, EEPROM loaded */
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return 0;
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}
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if (rom == NULL) {
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printk(BIOS_ERR, "No configuration data specified, using default MAC!\n");
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n.mac_address[0] = 0x0;
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n.mac_address[1] = 0x0;
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n.mac_address[2] = 0xde;
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n.mac_address[3] = 0xad;
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n.mac_address[4] = 0xbe;
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n.mac_address[5] = 0xef;
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n.phy_addr = 0x1;
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n.res1 = 0x0;
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n.sub_sid = 0x102;
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n.sub_vid = 0x1106;
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n.pid = 0x3065;
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n.vid = 0x1106;
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n.pmcc = 0x1f;
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n.data_sel = 0x10;
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n.pmu_data_reg = 0x0;
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n.aux_curr = 0x0;
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n.reserved = 0x0;
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n.min_gnt = 0x3;
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n.max_lat = 0x8;
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n.bcr0 = 0x9;
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n.bcr1 = 0xe;
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n.cfg_a = 0x3;
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n.cfg_b = 0x0;
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n.cfg_c = 0x40;
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n.cfg_d = 0x82;
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n.checksum = 0x0;
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rom = &n;
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}
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rom_write = (u16 *) rom;
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checksum = 0;
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/* write all data except checksum and second to last byte */
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tmp &= 0xff000000; /* leave reserved bits in */
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for (i = 0; i < 15; i++) {
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pci_conf1_write_config32(dev, 0x58, tmp | (i << 16) | rom_write[i]);
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/* lame code fixme */
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checksum += rom_write[i] & 0xff;
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//checksum %= 256;
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checksum += (rom_write[i] >> 8) & 0xff;
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//checksum %= 256;
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}
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checksum += (rom_write[15] & 0xff);
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checksum = ~(checksum & 0xff);
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tmp |= (((checksum & 0xff) << 8) | rom_write[15]);
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/* write last byte and checksum */
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pci_conf1_write_config32(dev, 0x58, (15 << 16) | tmp);
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tmp = pci_conf1_read_config32(dev, 0x5c);
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pci_conf1_write_config32(dev, 0x5c, tmp | 0x01000000); /* toggle SEEPR */
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/* Yes, this is a mess, but it's the easiest way to do it. */
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while ( (((pci_conf1_read_config32(dev, 0x5c) >> 25) & 1) == 0)
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&& (loops < LAN_TIMEOUT))
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++loops;
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if (loops >= LAN_TIMEOUT) {
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printk(BIOS_ERR, "Timout - LAN controller did not accept configuration\n");
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return 0;
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}
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/* we are done, config will be used after PCIRST# */
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return 1;
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}
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90
southbridge/via/vt8237/vt8237.h
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90
southbridge/via/vt8237/vt8237.h
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License v2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*
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* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SOUTHBRIDGE_VIA_VT8237_VT8237_H
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#define SOUTHBRIDGE_VIA_VT8237_VT8237_H
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#include <types.h>
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/* Static resources for the VT8237R southbridge */
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#define VT8237R_APIC_ID 0x2
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#define VT8237R_ACPI_IO_BASE 0x500
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/* 0x0 disabled, 0x2 reserved, 0xf = IRQ15 */
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#define VT8237R_ACPI_IRQ 0x9
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#define VT8237S_SPI_MEM_BASE 0xfed02000ULL
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#define VT8237R_HPET_ADDR 0xfed00000ULL
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#define VT8237R_APIC_BASE 0xfec00000ULL
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/* IDE */
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#define IDE_CS 0x40
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#define IDE_CONF_I 0x41
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#define IDE_CONF_II 0x42
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#define IDE_CONF_FIFO 0x43
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#define IDE_MISC_I 0x44
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#define IDE_MISC_II 0x45
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#define IDE_UDMA 0x50
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/* SMBus */
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#define VT8237R_POWER_WELL 0x94
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#define VT8237R_SMBUS_IO_BASE_REG 0xd0
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#define VT8237R_SMBUS_HOST_CONF 0xd2
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#define SMBHSTSTAT 0x0
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#define SMBSLVSTAT 0x1
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#define SMBHSTCTL 0x2
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#define SMBHSTCMD 0x3
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#define SMBXMITADD 0x4
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#define SMBHSTDAT0 0x5
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#define HOST_RESET 0xff
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/* 1 in the 0 bit of SMBHSTADD states to READ. */
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#define READ_CMD 0x01
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#define SMBUS_TIMEOUT (100 * 1000 * 10)
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#define I2C_TRANS_CMD 0x40
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#define CLOCK_SLAVE_ADDRESS 0x69
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struct vt8237_network_rom {
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u8 mac_address[6];
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u8 phy_addr;
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u8 res1;
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u16 sub_sid;
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u16 sub_vid;
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u16 pid;
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u16 vid;
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u8 pmcc;
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u8 data_sel;
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u8 pmu_data_reg;
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u8 aux_curr;
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u16 reserved;
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u8 min_gnt;
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u8 max_lat;
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u8 bcr0;
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u8 bcr1;
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u8 cfg_a;
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u8 cfg_b;
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u8 cfg_c;
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u8 cfg_d;
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u8 checksum;
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} __attribute__ ((packed));
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void enable_smbus(u16);
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u8 smbus_read_byte(u16, u8, u16);
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#endif
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