From 2d0cd2190b1f394dc9ac1ee7844942575a520be1 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 7 Oct 2013 16:29:54 -0700 Subject: [PATCH] lynxpoint: Export pch_enable_lpc() for SuperIO systems In order to enable a SuperIO in non ChromeEC systems we need to make pch_enable_lpc() available to the mainboard romstage.c BUG=none BRANCH=none TEST=boot ChromeOS on Beltino Change-Id: I34e7d23012e1852c69e82ba7cdc81a05751846de Signed-off-by: Stefan Reinauer Reviewed-on: https://chromium-review.googlesource.com/172180 Reviewed-by: Duncan Laurie Reviewed-by: Aaron Durbin Commit-Queue: Stefan Reinauer --- src/southbridge/intel/lynxpoint/early_pch.c | 2 +- src/southbridge/intel/lynxpoint/pch.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index df7358e04d..a5c12bfc2d 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -90,7 +90,7 @@ static int sleep_type_s3(void) return is_s3; } -static void pch_enable_lpc(void) +void pch_enable_lpc(void) { const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); const struct southbridge_intel_lynxpoint_config *config = NULL; diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index a1a6f6383f..982ccb3d8b 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -213,6 +213,7 @@ int smbus_read_byte(unsigned device, unsigned address); int early_spi_read(u32 offset, u32 size, u8 *buffer); int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); +void pch_enable_lpc(void); #endif /* !__PRE_RAM__ && !__SMM__ */ #endif /* __ASSEMBLER__ */