From 2ce567f1d04253e28e9c0460fff873822a4cc6f8 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Thu, 21 Mar 2024 12:38:52 -0600 Subject: [PATCH] soc/intel/common/block/cse: Prevent HECI commands when flash descriptor override is set MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sending the disable and EOP commands will not work if flash descriptor override is set on Meteor Lake. Change-Id: I3b5a56229434c9cc326141d48359faa7759541ee Signed-off-by: Jeremy Soller Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/82728 Tested-by: build bot (Jenkins) Reviewed-by: Michał Kopeć --- src/soc/intel/common/block/cse/cse.c | 8 ++++++++ src/soc/intel/common/block/cse/cse_eop.c | 6 ++++++ src/soc/intel/common/block/fast_spi/fast_spi.c | 9 +++++++++ .../intel/common/block/include/intelblocks/fast_spi.h | 4 ++++ 4 files changed, 27 insertions(+) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 55dd3d2da7..29a0c2192b 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -1348,6 +1349,13 @@ static void cse_set_state(struct device *dev) int send; int result; + + if (fast_spi_flash_descriptor_override()) { + printk(BIOS_WARNING, "HECI: not setting ME state because " + "flash descriptor override is enabled\n"); + return; + } + /* * Check if the CMOS value "me_state" exists, if it doesn't, then * don't do anything. diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 265fe04bbc..f2701d52da 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -243,6 +244,11 @@ static void do_send_end_of_post(bool wait_for_completion) return; } + if (fast_spi_flash_descriptor_override()) { + printk(BIOS_WARNING, "CSE: not sending EOP because flash descriptor override is enabled\n"); + return; + } + if (!eop_sent) { set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); timestamp_add_now(TS_ME_END_OF_POST_START); diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 45519611ab..8cff0707b6 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -472,6 +472,15 @@ void fast_spi_clear_outstanding_status(void) write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS); } +/* Check if flash descriptor override is asserted */ +bool fast_spi_flash_descriptor_override(void) +{ + void *spibar = fast_spi_get_bar(); + uint32_t hsfsts = read32(spibar + SPIBAR_HSFSTS_CTL); + printk(BIOS_DEBUG, "HSFSTS: 0x%X\n", hsfsts); + return !(hsfsts & SPIBAR_HSFSTS_FDOPSS); +} + /* As there is no official ACPI ID for this controller use the generic PNP ID for now. */ static const char *fast_spi_acpi_hid(const struct device *dev) diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 716f16a07a..6c28f25430 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -107,5 +107,9 @@ void fast_spi_cache_ext_bios_postcar(struct postcar_frame *pcf); * Set FAST_SPIBAR BIOS Decode Lock bit */ void fast_spi_set_bde(void); +/* + * Check if flash descriptor override is asserted + */ +bool fast_spi_flash_descriptor_override(void); #endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */