soc/mediatek/mt8186: Add DEVAPC settings for ADSP
Add DEVAPC permission settings for ADSP and set its domain number to 6. TEST=SOF driver is functional. BUG=b:204229221 Change-Id: I37bfea70386af953e89f3c38ac51e41af6aafa6e Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68290 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tinghan Shen
Felix Held
parent
a9e595770f
commit
2caa2fc56e
4 changed files with 151 additions and 3 deletions
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@ -36,6 +36,7 @@
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#define FORBIDDEN5 FORBIDDEN4, FORBIDDEN
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#define FORBIDDEN6 FORBIDDEN5, FORBIDDEN
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#define FORBIDDEN7 FORBIDDEN6, FORBIDDEN
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#define FORBIDDEN9 FORBIDDEN7, FORBIDDEN2
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#define FORBIDDEN10 FORBIDDEN3, FORBIDDEN7
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#define FORBIDDEN11 FORBIDDEN10, FORBIDDEN
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#define FORBIDDEN12 FORBIDDEN11, FORBIDDEN
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@ -10,7 +10,7 @@ static const struct apc_infra_peri_dom_8 infra_ao_sys0_devices[] = {
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/* 0 */
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DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_TOPCKGEN",
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NO_PROTECTION, FORBIDDEN3,
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NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION),
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NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
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DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_INFRASYS_CONFIG_REGS",
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NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION,
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FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN),
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@ -40,7 +40,7 @@ static const struct apc_infra_peri_dom_8 infra_ao_sys0_devices[] = {
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NO_PROTECTION, FORBIDDEN7),
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DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_APMIXEDSYS",
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NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
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NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION),
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NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
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DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PMIC_WRAP",
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NO_PROTECTION, NO_PROTECTION, FORBIDDEN3,
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NO_PROTECTION, NO_PROTECTION, FORBIDDEN),
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@ -366,7 +366,7 @@ static const struct apc_infra_peri_dom_8 infra_ao_sys0_devices[] = {
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/* 150 */
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DAPC_INFRA_AO_SYS0_ATTR("PERISYS_AUDIODSP",
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NO_PROTECTION, FORBIDDEN7),
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN),
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};
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/* module, AP permission, N/A, SSPM permission, N/A */
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@ -1183,6 +1183,88 @@ static const struct apc_infra_peri_dom_4 mm_ao_sys0_devices[] = {
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NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION),
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};
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static const struct apc_infra_peri_dom_16 adsp_ao_sys0_devices[] = {
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/* 0 */
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_INFRA",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_INFRA_1",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_INFRA_2",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_EMI",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_AFE",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_AFE_1",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DSP1",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DSP1_1",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DSP2",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DSP2_1",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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/* 10 */
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_F_SRAM",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_H_SRAM",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DSPCFG",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DSPCKCTL",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DMA0_CFG",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DSP_TIMER",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DSP_UART",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_BUSMON_DRAM",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DSPMBOX_0",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DSPMBOX_1",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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/* 20 */
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DSPMBOX_2",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DSPMBOX_3",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DSPMBOX_4",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DSPCFG_SEC",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_BUSMON_INFRA",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DMA1_CFG",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_RESERVED",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_BUSCFG",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_TMBIST",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_BCRM",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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/* 30 */
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_BUS_DEBUG",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_SYSCFG_AO",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_MASRC",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DAPC_AO",
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SEC_RW_ONLY, FORBIDDEN15),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_K_BCRM",
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NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN9),
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DAPC_AUD_AO_SYS0_ATTR("AUD_AO_DAPC",
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SEC_RW_ONLY, FORBIDDEN15),
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};
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static const enum domain_id domain_map[] = {
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DOMAIN_0, DOMAIN_1, DOMAIN_2, DOMAIN_3,
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DOMAIN_4, DOMAIN_5, DOMAIN_6, DOMAIN_7,
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@ -1218,6 +1300,37 @@ static void set_mm_ao_apc(uintptr_t base)
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mm_ao_sys0_devices[i].d_permission[j]);
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}
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#define AUD_DOMAIN_OFT 0x40
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static void *adsp_getreg_domain(uintptr_t base, unsigned int offset,
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enum domain_id domain_id, unsigned int index)
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{
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return (void *)(base + offset + domain_id * AUD_DOMAIN_OFT + index * IDX_OFT);
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}
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static void adsp_set_module_apc(uintptr_t base, uint32_t module, enum domain_id domain_id,
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enum devapc_perm_type perm)
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{
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uint32_t apc_register_index;
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uint32_t apc_set_index;
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apc_register_index = module / MOD_NO_IN_1_DEVAPC;
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apc_set_index = module % MOD_NO_IN_1_DEVAPC;
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clrsetbits32(adsp_getreg_domain(base, 0, domain_id, apc_register_index),
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0x3 << (apc_set_index * 2),
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perm << (apc_set_index * 2));
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}
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static void set_adsp_ao_apc(uintptr_t base)
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{
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int i, j;
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for (i = 0; i < ARRAY_SIZE(adsp_ao_sys0_devices); i++)
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for (j = 0; j < ARRAY_SIZE(adsp_ao_sys0_devices[i].d_permission); j++)
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adsp_set_module_apc(base + SYS0_D0_APC_0, i, domain_map[j],
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adsp_ao_sys0_devices[i].d_permission[j]);
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}
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static void dump_infra_ao_apc(uintptr_t base)
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{
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int reg_max;
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@ -1248,6 +1361,24 @@ static void dump_mm_ao_apc(uintptr_t base)
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read32(getreg(base, MAS_SEC_0)));
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}
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static void dump_adsp_ao_apc(uintptr_t base)
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{
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int reg_max;
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unsigned int d, i;
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reg_max = DIV_ROUND_UP(ARRAY_SIZE(adsp_ao_sys0_devices), MOD_NO_IN_1_DEVAPC);
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for (d = 0; d < DOM_NUM_AUD_AO_SYS0; d++)
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for (i = 0; i < reg_max; i++)
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printk(BIOS_DEBUG, "[DEVAPC] (AUD_AO_SYS0)D%d_APC_%d: %#x\n", d, i,
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read32(adsp_getreg_domain(base, SYS0_D0_APC_0, d, i)));
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printk(BIOS_DEBUG, "[DEVAPC] (AUD_AO)MAS_0: %#x\n",
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read32(getreg(base, AUD_DOM_0)));
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printk(BIOS_DEBUG, "[DEVAPC] (AUD_AO)SEC_0: %#x\n",
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read32(getreg(base, AUD_SEC_0)));
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}
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static void infra_init(uintptr_t base)
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{
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/* Side band */
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@ -1281,6 +1412,15 @@ static void mm_init(uintptr_t base)
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TWO_BIT_DOM_REMAP_5, DOMAIN_2);
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}
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static void adsp_init(uintptr_t base)
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{
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set_adsp_ao_apc(base);
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/* Master domain/secure */
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SET32_BITFIELDS(getreg(base, AUD_DOM_0), ADSP_DOM, DOMAIN_6);
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write32(getreg(base, AUD_SEC_0), 0);
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}
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struct devapc_init_ops {
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uintptr_t base;
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void (*init)(uintptr_t base);
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@ -1288,6 +1428,7 @@ struct devapc_init_ops {
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} devapc_init[] = {
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{ DEVAPC_AO_INFRA_PERI_BASE, infra_init, dump_infra_ao_apc },
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{ DEVAPC_AO_MM_BASE, mm_init, dump_mm_ao_apc },
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{ DEVAPC_AO_AUD_BASE, adsp_init, dump_adsp_ao_apc },
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};
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void dapc_init(void)
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@ -51,6 +51,7 @@ enum {
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SSPM_SRAM_BASE = IO_PHYS + 0x00400000,
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SSPM_CFG_BASE = IO_PHYS + 0x00440000,
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AUDIODSP_BASE = IO_PHYS + 0x00680000,
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DEVAPC_AO_AUD_BASE = IO_PHYS + 0x0069C000,
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SFLASH_REG_BASE = IO_PHYS + 0x01000000,
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AUXADC_BASE = IO_PHYS + 0x01001000,
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UART0_BASE = IO_PHYS + 0x01002000,
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@ -19,6 +19,8 @@ enum devapc_ao_offset {
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MAS_DOM_3 = 0x0A0C,
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MAS_SEC_0 = 0x0B00,
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AO_APC_CON = 0x0F00,
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AUD_DOM_0 = 0x0900,
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AUD_SEC_0 = 0x0A00,
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};
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/******************************************************************************
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@ -39,6 +41,7 @@ struct apc_infra_peri_dom_4 {
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enum devapc_sys_dom_num {
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DOM_NUM_INFRA_AO_SYS0 = 8,
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DOM_NUM_MM_AO_SYS0 = 4,
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DOM_NUM_AUD_AO_SYS0 = 16,
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};
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enum devapc_cfg_index {
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@ -48,6 +51,7 @@ enum devapc_cfg_index {
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/* PERM_ATTR MACRO */
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#define DAPC_INFRA_AO_SYS0_ATTR(...) { { DAPC_PERM_ATTR_8(__VA_ARGS__) } }
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#define DAPC_MM_AO_SYS0_ATTR(...) { { DAPC_PERM_ATTR_4(__VA_ARGS__) } }
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#define DAPC_AUD_AO_SYS0_ATTR(...) { { DAPC_PERM_ATTR_16(__VA_ARGS__) } }
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/******************************************************************************
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* Variable DEFINITION
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@ -62,6 +66,7 @@ enum devapc_cfg_index {
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DEFINE_BIT(SCP_SSPM_SEC, 21)
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DEFINE_BITFIELD(SPM_DOM, 11, 8)
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DEFINE_BITFIELD(SCP_DOM, 3, 0)
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DEFINE_BITFIELD(ADSP_DOM, 3, 0)
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/* Domain Remap */
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DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_0, 1, 0)
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