From 2c9dfe61bd85842664ff904f187c8300597a9ebd Mon Sep 17 00:00:00 2001
From: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Date: Wed, 10 Aug 2016 11:33:56 -0700
Subject: [PATCH] UPSTREAM: soc/apollolake: enable access to RTC NVRAM

FSP unconditionally locks parts of the NVRAM in the RTC.
This change will enable coreboot to update the locking policy
and be able to unlock the region

BUG=chrome-os-partner:55944
BRANCH=None

TEST=Check 'crossystem dev_boot_usb=1'

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/16144
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>

Change-Id: I70fd2bafa6ff9eb9cdf284b9780e4b90dee0f4ce
Reviewed-on: https://chromium-review.googlesource.com/369150
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/apollolake/chip.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 345d7c4446..1b109d0c93 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -397,6 +397,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
 
 	/* Disable setting of EISS bit in FSP. */
 	silconfig->SpiEiss = 0;
+
+	/* Disable FSP from locking access to the RTC NVRAM */
+	silconfig->RtcLock = 0;
 }
 
 struct chip_operations soc_intel_apollolake_ops = {