From 2c4f703f0b87d8642e9e77967a54023c27e63886 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Fri, 10 May 2002 17:10:14 +0000 Subject: [PATCH] $PIR support for the lippert roadrunner 2 --- src/mainboard/lippert/roadrunner2/Config | 2 ++ .../lippert/roadrunner2/irq_tables.c | 30 +++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 src/mainboard/lippert/roadrunner2/irq_tables.c diff --git a/src/mainboard/lippert/roadrunner2/Config b/src/mainboard/lippert/roadrunner2/Config index 68bb62f52d..2f35b54a2c 100644 --- a/src/mainboard/lippert/roadrunner2/Config +++ b/src/mainboard/lippert/roadrunner2/Config @@ -56,6 +56,8 @@ option NO_KEYBOARD option FINAL_MAINBOARD_FIXUP=1 object mainboard.o option ZKERNEL_START=0xfffc0000 +object irq_tables.o +option HAVE_PIRQ_TABLE=1 # Local variables: # compile-command: "make -C /export/bios/voyager2" diff --git a/src/mainboard/lippert/roadrunner2/irq_tables.c b/src/mainboard/lippert/roadrunner2/irq_tables.c new file mode 100644 index 0000000000..810e1b394c --- /dev/null +++ b/src/mainboard/lippert/roadrunner2/irq_tables.c @@ -0,0 +1,30 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ + +#include + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*6, /* there can be total 6 devices on the bus */ + 0, /* Where the interrupt router lies (bus) */ + 0x90, /* Where the interrupt router lies (dev) */ + 0x800, /* IRQs devoted exclusively to PCI usage */ + 0x1078, /* Vendor */ + 0x2, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x3b, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + {0,0x70, {{0x2, 0xdeb8}, {0x1, 0xdeb8}, {0x4, 0xdeb8}, {0x3, 0xdeb8}}, 0x1, 0}, + {0,0x78, {{0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}, {0x4, 0xdeb8}}, 0x2, 0}, + {0,0x68, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0}, + {0,0x60, {{0x1, 0xdeb8}, {0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}}, 0x4, 0}, + {0,0x88, {{0x4, 0xdeb8}, {0x4, 0xdeb8}, {0x4, 0xdeb8}, {0x4, 0xdeb8}}, 0x5, 0}, + {0,0x80, {{0x1, 0xdeb8}, {0x1, 0xdeb8}, {0x1, 0xdeb8}, {0x1, 0xdeb8}}, 0, 0}, + } +};