From 2c4af7cd29ab1eb1975e614635d4ea1a0d653aac Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Tue, 17 Dec 2024 04:07:35 +0100
Subject: [PATCH] mb/topton/adl: Enable TPM2 (Intel fTPM/PTT)

Change-Id: If1a52cacf2eeef68efdd98c48d5802712305f354
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/topton/adl/Kconfig       | 2 ++
 src/mainboard/topton/adl/devicetree.cb | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/src/mainboard/topton/adl/Kconfig b/src/mainboard/topton/adl/Kconfig
index 94cd222a67..df8a513725 100644
--- a/src/mainboard/topton/adl/Kconfig
+++ b/src/mainboard/topton/adl/Kconfig
@@ -13,6 +13,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_ALDERLAKE_PCH_N
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select HAVE_INTEL_PTT
+	select CRB_TPM
 
 config MAINBOARD_DIR
 	default "topton/adl"
diff --git a/src/mainboard/topton/adl/devicetree.cb b/src/mainboard/topton/adl/devicetree.cb
index 5dcca690b4..2b8ac2b8ce 100644
--- a/src/mainboard/topton/adl/devicetree.cb
+++ b/src/mainboard/topton/adl/devicetree.cb
@@ -118,5 +118,8 @@ chip soc/intel/alderlake
 			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"
 			register "pch_hda_idisp_link_tmode"		= "HDA_TMODE_8T"
 		end
+		chip drivers/crb
+			device mmio 0xfed40000 on end
+		end
 	end
 end