AGESA F15 wrapper for Trinity
The wrapper for Trinity. Support S3. Parme is a example board. Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1156 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
zbao
Patrick Georgi
parent
7d94cf93ee
commit
2c08f6ade4
25 changed files with 2399 additions and 8 deletions
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@ -23,6 +23,7 @@ config CPU_AMD_AGESA
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default y if CPU_AMD_AGESA_FAMILY12
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default y if CPU_AMD_AGESA_FAMILY14
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default y if CPU_AMD_AGESA_FAMILY15
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default y if CPU_AMD_AGESA_FAMILY15_TN
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default n
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if CPU_AMD_AGESA
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@ -42,6 +43,6 @@ source src/cpu/amd/agesa/family10/Kconfig
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source src/cpu/amd/agesa/family12/Kconfig
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source src/cpu/amd/agesa/family14/Kconfig
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source src/cpu/amd/agesa/family15/Kconfig
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source src/cpu/amd/agesa/family15tn/Kconfig
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endif # CPU_AMD_AGESA
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@ -20,6 +20,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
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romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c
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ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c
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@ -32,7 +32,7 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/amdfam15.h>
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static msr_t rdmsr_amd(u32 index)
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msr_t rdmsr_amd(u32 index)
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{
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msr_t result;
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__asm__ __volatile__(
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@ -43,7 +43,7 @@ static msr_t rdmsr_amd(u32 index)
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return result;
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}
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static void wrmsr_amd(u32 index, msr_t msr)
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void wrmsr_amd(u32 index, msr_t msr)
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{
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__asm__ __volatile__(
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"wrmsr"
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79
src/cpu/amd/agesa/family15tn/Kconfig
Normal file
79
src/cpu/amd/agesa/family15tn/Kconfig
Normal file
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@ -0,0 +1,79 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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config CPU_AMD_AGESA_FAMILY15_TN
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bool
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select PCI_IO_CFG_EXT
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config CPU_ADDR_BITS
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int
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default 36
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config CPU_SOCKET_TYPE
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hex
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default 0x10
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depends on CPU_AMD_AGESA_FAMILY15_TN
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# DDR2 and REG
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config DIMM_SUPPORT
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hex
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default 0x0104
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config EXT_RT_TBL_SUPPORT
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bool
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default n
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config EXT_CONF_SUPPORT
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bool
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default n
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config CBB
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hex
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default 0x0
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config CDB
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hex
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default 0x18
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config XIP_ROM_BASE
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hex
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default 0xfff80000
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config XIP_ROM_SIZE
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hex
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default 0x100000
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config HAVE_INIT_TIMER
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bool
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default y
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depends on CPU_AMD_AGESA_FAMILY15_TN
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config HIGH_SCRATCH_MEMORY_SIZE
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hex
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# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
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default 0xA1000
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depends on CPU_AMD_AGESA_FAMILY15_TN
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466
src/cpu/amd/agesa/family15tn/Makefile.inc
Normal file
466
src/cpu/amd/agesa/family15tn/Makefile.inc
Normal file
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@ -0,0 +1,466 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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ramstage-y += chip_name.c
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driver-y += model_15_init.c
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AGESA_ROOT = ../../../../vendorcode/amd/agesa/f15tn
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agesa_lib_src =
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agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c
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agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c
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agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c
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agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c
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agesa_lib_src += $(AGESA_ROOT)/Lib/helper.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnC6State.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnCpb.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPciTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnUtilities.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15BrandId.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15Dmi.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15MmioMap.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15MsrTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15PciTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15PowerCheck.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15Utilities.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/PreserveMailbox.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuC6State.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCoreLeveling.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCpb.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuDmi.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatures.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHtc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHwC1e.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPsi.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateGather.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateLeveling.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSlit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSrat.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuWhea.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/S3.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Table.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBist.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBrandId.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEarlyInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEventLog.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuFamilyTranslation.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuGeneralServices.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuLateInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuMicrocodePatch.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPostInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmt.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtMultiSocket.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtSingleSocket.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuWarmReset.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/heapManager.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEarly.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEnv.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitMid.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitPost.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitReset.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitResume.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdLateRunApTask.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3LateRestore.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3Save.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonInits.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonReturns.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CreateStruct.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3RestoreState.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3SaveState.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Common/GnbLibFeatures.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEarly.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtMid.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtPost.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtReset.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtS3Save.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSview/GnbSview.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbTable/GnbTable.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbFam15Mod1x.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterface.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceCoherent.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceGeneral.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceNonCoherent.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htMain.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNb.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNotify.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Control/IdsCtrl.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebug.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebugPrint.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDpSerial.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Library/IdsLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ma.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CSINTLV/mfcsi.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/DMI/mfDMI.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfecc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfemp.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/MEMCLR/mfmemclr.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/S3/mfs3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/TABLE/mftds.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/TN/mmflowtn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mdef.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/merrhdl.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mm.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmConditionalPso.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmEcc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmExcludeDimm.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmLvDdr3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemClr.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemRestore.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmNodeInterleave.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmOnlineSpare.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmStandardTraining.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmUmaAlloc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmflow.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mu.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/muc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mndcttn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnflowtn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnidendimmtn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnmcttn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnottn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnphytn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnregtn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mns3tn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mntn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnS3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mndct.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnfeat.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnmct.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnphy.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mntrain3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FM2/mpUtnfm2.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FP2/mpStnfp2.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FS1/mpStnfs1.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mpStn3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mpUtn3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mptn3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mp.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpmaxfreq.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpmr0.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpodtpat.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mprtt.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpsao.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mt3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtot3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtrci3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtsdi3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtspd3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttecc3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttwl3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mthdi.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttEdgeDetect.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttdimbt.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttecc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrcSeedTrain.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttml.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttoptsrc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttsrc.c
|
||||
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/AcpiLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchCommon.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchPeLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/MemLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/PciLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ide/IdeEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ide/IdeLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ide/IdeMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitS3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchTaskLauncher.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/InitEnvDef.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/InitResetDef.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ir/IrEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ir/IrLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ir/IrMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppHp.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppPortInit.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataEnvLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataLib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdResetService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/SdEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/SdLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/SdMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbReset.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciLate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciMid.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciReset.c
|
||||
|
||||
|
||||
romstage-y += $(agesa_lib_src)
|
||||
ramstage-y += $(agesa_lib_src)
|
||||
|
||||
subdirs-y += ../../mtrr
|
||||
subdirs-y += ../../../x86/tsc
|
||||
subdirs-y += ../../../x86/lapic
|
||||
subdirs-y += ../../../x86/cache
|
||||
subdirs-y += ../../../x86/mtrr
|
||||
subdirs-y += ../../../x86/pae
|
||||
subdirs-y += ../../../x86/smm
|
||||
23
src/cpu/amd/agesa/family15tn/chip.h
Normal file
23
src/cpu/amd/agesa/family15tn/chip.h
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
extern struct chip_operations cpu_amd_agesa_family15tn_ops;
|
||||
|
||||
struct cpu_amd_agesa_family15tn_config {
|
||||
};
|
||||
25
src/cpu/amd/agesa/family15tn/chip_name.c
Normal file
25
src/cpu/amd/agesa/family15tn/chip_name.c
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations cpu_amd_agesa_family15tn_ops = {
|
||||
CHIP_NAME("AMD CPU Family 15h")
|
||||
};
|
||||
151
src/cpu/amd/agesa/family15tn/model_15_init.c
Normal file
151
src/cpu/amd/agesa/family15tn/model_15_init.c
Normal file
|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/pae.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/amd/amdfam15.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <cpu/amd/agesa/s3_resume.h>
|
||||
|
||||
msr_t rdmsr_amd(u32 index)
|
||||
{
|
||||
msr_t result;
|
||||
__asm__ __volatile__(
|
||||
"rdmsr"
|
||||
:"=a"(result.lo), "=d"(result.hi)
|
||||
:"c"(index), "D"(0x9c5a203a)
|
||||
);
|
||||
return result;
|
||||
}
|
||||
|
||||
void wrmsr_amd(u32 index, msr_t msr)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"wrmsr"
|
||||
: /* No outputs */
|
||||
:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
|
||||
);
|
||||
}
|
||||
|
||||
static void model_15_init(device_t dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Model 15 Init.\n");
|
||||
|
||||
u8 i;
|
||||
msr_t msr;
|
||||
int msrno;
|
||||
#if CONFIG_LOGICAL_CPUS == 1
|
||||
u32 siblings;
|
||||
#endif
|
||||
|
||||
//x86_enable_cache();
|
||||
//amd_setup_mtrrs();
|
||||
//x86_mtrr_check();
|
||||
disable_cache ();
|
||||
/* Enable access to AMD RdDram and WrDram extension bits */
|
||||
msr = rdmsr(SYSCFG_MSR);
|
||||
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
|
||||
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
|
||||
wrmsr(SYSCFG_MSR, msr);
|
||||
|
||||
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
|
||||
msr.lo = msr.hi = 0;
|
||||
wrmsr (0x259, msr);
|
||||
msr.lo = msr.hi = 0x1e1e1e1e;
|
||||
wrmsr(0x250, msr);
|
||||
wrmsr(0x258, msr);
|
||||
for (msrno = 0x268; msrno <= 0x26f; msrno++)
|
||||
wrmsr (msrno, msr);
|
||||
|
||||
msr = rdmsr(SYSCFG_MSR);
|
||||
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
|
||||
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
|
||||
wrmsr(SYSCFG_MSR, msr);
|
||||
|
||||
#if CONFIG_HAVE_ACPI_RESUME == 1
|
||||
if (acpi_slp_type == 3)
|
||||
restore_mtrr();
|
||||
#endif
|
||||
|
||||
x86_mtrr_check();
|
||||
x86_enable_cache();
|
||||
|
||||
/* zero the machine check error status registers */
|
||||
msr.lo = 0;
|
||||
msr.hi = 0;
|
||||
for (i = 0; i < 6; i++) {
|
||||
wrmsr(MCI_STATUS + (i * 4), msr);
|
||||
}
|
||||
|
||||
|
||||
/* Enable the local cpu apics */
|
||||
setup_lapic();
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS == 1
|
||||
siblings = cpuid_ecx(0x80000008) & 0xff;
|
||||
|
||||
if (siblings > 0) {
|
||||
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
|
||||
msr.lo |= 1 << 28;
|
||||
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
|
||||
|
||||
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
|
||||
msr.hi |= 1 << (33 - 32);
|
||||
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
|
||||
}
|
||||
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
|
||||
#endif
|
||||
|
||||
/* DisableCf8ExtCfg */
|
||||
msr = rdmsr(NB_CFG_MSR);
|
||||
msr.hi &= ~(1 << (46 - 32));
|
||||
wrmsr(NB_CFG_MSR, msr);
|
||||
|
||||
|
||||
/* Write protect SMM space with SMMLOCK. */
|
||||
msr = rdmsr(HWCR_MSR);
|
||||
msr.lo |= (1 << 0);
|
||||
wrmsr(HWCR_MSR, msr);
|
||||
}
|
||||
|
||||
static struct device_operations cpu_dev_ops = {
|
||||
.init = model_15_init,
|
||||
};
|
||||
|
||||
static struct cpu_device_id cpu_table[] = {
|
||||
{ X86_VENDOR_AMD, 0x610f00 }, /* TN-A0 */
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static const struct cpu_driver model_15 __cpu_driver = {
|
||||
.ops = &cpu_dev_ops,
|
||||
.id_table = cpu_table,
|
||||
};
|
||||
|
|
@ -225,6 +225,8 @@ void OemAgesaSaveMtrr(void)
|
|||
dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi);
|
||||
nvram_pos += 4;
|
||||
|
||||
write_spi_status((u8 *)spi_address, 0x3c);
|
||||
spi_write_disable((u8 *) spi_address);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -273,6 +275,10 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
|
|||
S3_DATA_VOLATILE_POS + 0x2000);
|
||||
sector_erase_spi((u8 *) spi_address,
|
||||
S3_DATA_VOLATILE_POS + 0x3000);
|
||||
sector_erase_spi((u8 *) spi_address,
|
||||
S3_DATA_VOLATILE_POS + 0x4000);
|
||||
sector_erase_spi((u8 *) spi_address,
|
||||
S3_DATA_VOLATILE_POS + 0x5000);
|
||||
}
|
||||
|
||||
nvram_pos = 0;
|
||||
|
|
@ -283,6 +289,9 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
|
|||
dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos + 4,
|
||||
*(u32 *) (Data + nvram_pos));
|
||||
}
|
||||
/* write_spi_status((u8 *)spi_address, 0x3c); */
|
||||
|
||||
/* spi_write_disable((u8 *) spi_address); */
|
||||
|
||||
return AGESA_SUCCESS;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,9 +20,9 @@
|
|||
#ifndef S3_RESUME_H
|
||||
#define S3_RESUME_H
|
||||
|
||||
#define S3_DATA_NONVOLATILE_POS 0xFFFF4000
|
||||
#define S3_DATA_NONVOLATILE_POS 0xFFFF7000
|
||||
#define S3_DATA_VOLATILE_POS 0xFFFF0000
|
||||
#define S3_DATA_MTRR_POS 0xFFFF3100
|
||||
#define S3_DATA_MTRR_POS 0xFFFF6000
|
||||
|
||||
typedef enum {
|
||||
S3DataTypeNonVolatile=0, ///< NonVolatile Data Type
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue