- First pass at s2880 support.
- SMP cleanups (remove SMP only use CONFIG_SMP) - Minor tweaks to romcc to keep it from taking forever compiling - failover fixes - Get a good implementation of k8_cpufixup and sizeram for the opteron git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
6d4512cdf9
commit
2c018fba95
33 changed files with 1513 additions and 269 deletions
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@ -86,6 +86,11 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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return ret;
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/amdk8/cpu_ldtstop.c"
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#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
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@ -25,6 +25,12 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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return 0x00010101; /* default row entry */
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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@ -17,7 +17,7 @@
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "debug.c"
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static void memreset_setup(const struct mem_controller *ctrl)
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static void memreset_setup(void)
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{
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/* Set the memreset low */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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@ -25,12 +25,12 @@ static void memreset_setup(const struct mem_controller *ctrl)
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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}
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static void memreset(const struct mem_controller *ctrl)
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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udelay(800);
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/* Set memreset_high */
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
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udelay(50);
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udelay(90);
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}
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static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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@ -77,6 +77,11 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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return ret;
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/amdk8/cpu_ldtstop.c"
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#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
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@ -137,53 +142,64 @@ static void pc87360_enable_serial(void)
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pnp_set_iobase0(SIO_BASE, 0x3f8);
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}
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#define FIRST_CPU 1
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#define SECOND_CPU 0
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#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
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static void main(void)
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{
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/*
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* GPIO28 of 8111 will control H0_MEMRESET_L
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* GPIO29 of 8111 will control H1_MEMRESET_L
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*/
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static const struct mem_controller cpu0 = {
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.f0 = PCI_DEV(0, 0x18, 0),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f3 = PCI_DEV(0, 0x18, 3),
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.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
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.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
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};
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static const struct mem_controller cpu1 = {
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.f0 = PCI_DEV(0, 0x19, 0),
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.f1 = PCI_DEV(0, 0x19, 1),
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.f2 = PCI_DEV(0, 0x19, 2),
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.f3 = PCI_DEV(0, 0x19, 3),
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.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
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.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
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static const struct mem_controller cpu[] = {
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#if FIRST_CPU
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{
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.node_id = 0,
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.f0 = PCI_DEV(0, 0x18, 0),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f3 = PCI_DEV(0, 0x18, 3),
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.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
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.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
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},
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#endif
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#if SECOND_CPU
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{
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.node_id = 1,
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.f0 = PCI_DEV(0, 0x19, 0),
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.f1 = PCI_DEV(0, 0x19, 1),
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.f2 = PCI_DEV(0, 0x19, 2),
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.f3 = PCI_DEV(0, 0x19, 3),
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.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
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.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
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},
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#endif
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};
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if (cpu_init_detected()) {
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asm("jmp __cpu_reset");
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}
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pc87360_enable_serial();
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uart_init();
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console_init();
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enable_lapic();
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init_timer();
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if (!boot_cpu()) {
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stop_this_cpu();
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}
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init_timer();
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pc87360_enable_serial();
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uart_init();
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console_init();
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setup_default_resource_map();
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setup_coherent_ht_domain();
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enumerate_ht_chain(0);
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distinguish_cpu_resets();
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distinguish_cpu_resets(0);
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#if 1
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#if 0
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print_pci_devices();
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#endif
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enable_smbus();
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#if 0
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dump_spd_registers(&cpu0);
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dump_spd_registers(&cpu[0]);
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#endif
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sdram_initialize(&cpu0);
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memreset_setup();
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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#if 1
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dump_pci_devices();
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@ -204,7 +220,12 @@ static void main(void)
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#if 0
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ram_check(0x00000000, msr.lo);
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#else
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/* Check 16MB of memory */
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#if TOTAL_CPUS < 2
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/* Check 16MB of memory @ 0*/
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ram_check(0x00000000, 0x01000000);
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#else
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/* Check 16MB of memory @ 2GB */
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ram_check(0x80000000, 0x81000000);
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#endif
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#endif
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}
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134
src/mainboard/tyan/s2880/Config.lb
Normal file
134
src/mainboard/tyan/s2880/Config.lb
Normal file
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@ -0,0 +1,134 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses USE_NORMAL_IMAGE
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uses AMD8111_DEV
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#
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#
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###
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### Set all of the defaults for an x86 architecture
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###
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#
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#
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###
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### Build the objects we have code for in this directory.
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###
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##object mainboard.o
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driver mainboard.o
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object static_devices.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#
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arch i386 end
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cpu k8 end
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#
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###
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### Build our 16 bit and 32 bit linuxBIOS entry code
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###
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/i386/entry32.lds
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#
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###
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### Build our reset vector (This is where linuxBIOS is entered)
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###
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if USE_FALLBACK_IMAGE
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print "Use fallback!"
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mainboardinit cpu/i386/reset16.inc
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ldscript /cpu/i386/reset16.lds
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end
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if USE_NORMAL_IMAGE
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mainboardinit cpu/i386/reset32.inc
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ldscript /cpu/i386/reset32.lds
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end
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#
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#### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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#
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###
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### Include an id string (For safe flashing)
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###
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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#
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####
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#### This is the early phase of linuxBIOS startup
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#### Things are delicate and we test to see if we should
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#### failover to another image.
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####
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#option MAX_REBOOT_CNT=2
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##ldscript arch/i386/lib/failover.lds USE_FALLBACK_IMAGE
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#
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###
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### Setup our mtrrs
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###
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mainboardinit cpu/k8/earlymtrr.inc
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#
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#
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###
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### Only the bootstrap cpu makes it here.
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### Failover if we need to
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###
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#
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if USE_FALLBACK_IMAGE
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mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
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end
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#
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####
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#### O.k. We aren't just an intermediary anymore!
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####
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#
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###
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### When debugging disable the watchdog timer
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###
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##option MAXIMUM_CONSOLE_LOGLEVEL=7
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#default MAXIMUM_CONSOLE_LOGLEVEL=7
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#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
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#if DISABLE_WATCHDOG
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# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
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#end
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#
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###
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### Setup the serial port
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###
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#mainboardinit superiowinbond/w83627hf/setup_serial.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
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#
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###
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### Romcc output
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###
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#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
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#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
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#mainboardinit .failover.inc
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makerule ./auto.E dep "$(MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
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mainboardinit ./auto.inc
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#
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###
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### Setup RAM
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###
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mainboardinit ram/ramtest.inc
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mainboardinit southbridge/amd/amd8111/smbus.inc
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mainboardinit sdram/generic_dump_spd.inc
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#
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###
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### Include the secondary Configuration files
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###
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northbridge amd/amdk8
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end
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southbridge amd/amd8111
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end
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#mainboardinit archi386/smp/secondary.inc
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superio NSC/pc87360
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register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1"
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end
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dir /pc80
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##dir /src/superio/winbond/w83627hf
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cpu p5 end
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cpu p6 end
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cpu k7 end
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cpu k8 end
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1
src/mainboard/tyan/s2880/VERSION
Normal file
1
src/mainboard/tyan/s2880/VERSION
Normal file
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@ -0,0 +1 @@
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2.0
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437
src/mainboard/tyan/s2880/auto.c
Normal file
437
src/mainboard/tyan/s2880/auto.c
Normal file
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@ -0,0 +1,437 @@
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include "arch/romcc_io.h"
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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/*
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#warning "FIXME move these delay functions somewhere more appropriate"
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#warning "FIXME use the apic timer instead it needs no calibration on an Opteron it runs at 200Mhz"
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static void print_clock_multiplier(void)
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{
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msr_t msr;
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print_debug("clock multipler: 0x");
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msr = rdmsr(0xc0010042);
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print_debug_hex32(msr.lo & 0x3f);
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print_debug(" = 0x");
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print_debug_hex32(((msr.lo & 0x3f) + 8) * 100);
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print_debug("Mhz\r\n");
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}
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static unsigned usecs_to_ticks(unsigned usecs)
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{
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#warning "FIXME make usecs_to_ticks work properly"
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#if 1
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return usecs *2000;
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#else
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// This can only be done if cpuid says fid changing is supported
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// I need to look up the base frequency another way for other
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// cpus. Is it worth dedicating a global register to this?
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// Are the PET timers useable for this purpose?
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msr_t msr;
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msr = rdmsr(0xc0010042);
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return ((msr.lo & 0x3f) + 8) * 100 *usecs;
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#endif
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}
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static void init_apic_timer(void)
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{
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volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000;
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uint32_t start, end;
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// Set the apic timer to no interrupts and periodic mode
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apic_reg[0x320 >> 2] = (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0);
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// Set the divider to 1, no divider
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apic_reg[0x3e0 >> 2] = (1 << 3) | 3;
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// Set the initial counter to 0xffffffff
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apic_reg[0x380 >> 2] = 0xffffffff;
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}
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static void udelay(unsigned usecs)
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{
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#if 1
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uint32_t start, ticks;
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tsc_t tsc;
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// Calculate the number of ticks to run for
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ticks = usecs_to_ticks(usecs);
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// Find the current time
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tsc = rdtsc();
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start = tsc.lo;
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do {
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tsc = rdtsc();
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} while((tsc.lo - start) < ticks);
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#else
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volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000;
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uint32_t start, value, ticks;
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// Calculate the number of ticks to run for
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ticks = usecs * 200;
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start = apic_reg[0x390 >> 2];
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do {
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value = apic_reg[0x390 >> 2];
|
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} while((start - value) < ticks);
|
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#endif
|
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}
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static void mdelay(unsigned msecs)
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{
|
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int i;
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for(i = 0; i < msecs; i++) {
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udelay(1000);
|
||||
}
|
||||
}
|
||||
|
||||
static void delay(unsigned secs)
|
||||
{
|
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int i;
|
||||
for(i = 0; i < secs; i++) {
|
||||
mdelay(1000);
|
||||
}
|
||||
}
|
||||
|
||||
static void memreset_setup(const struct mem_controller *ctrl)
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{
|
||||
// Set the memreset low
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||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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// Ensure the BIOS has control of the memory lines
|
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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print_debug("memreset lo\r\n");
|
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}
|
||||
|
||||
static void memreset(const struct mem_controller *ctrl)
|
||||
{
|
||||
udelay(800);
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// Set memreset_high
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
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print_debug("memreset hi\r\n");
|
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udelay(50);
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||||
}
|
||||
*/
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
#define NODE_ID 0x60
|
||||
#define HT_INIT_CONTROL 0x6c
|
||||
|
||||
#define HTIC_ColdR_Detect (1<<4)
|
||||
#define HTIC_BIOSR_Detect (1<<5)
|
||||
#define HTIC_INIT_Detect (1<<6)
|
||||
|
||||
#define APIC_DEFAULT_BASE 0xfee00000
|
||||
|
||||
#define APIC_ID 0x020
|
||||
|
||||
static int boot_cpu(void)
|
||||
{
|
||||
volatile unsigned long *local_apic;
|
||||
unsigned long apic_id;
|
||||
int bsp;
|
||||
int apicEn;
|
||||
msr_t msr;
|
||||
msr = rdmsr(0x1b);
|
||||
bsp = !!(msr.lo & (1 << 8));
|
||||
apicEn = !!(msr.lo & (1<<11));
|
||||
if(apicEn) {
|
||||
print_debug("apic enabled\r\n");
|
||||
} else {
|
||||
msr.lo |= (1<<11);
|
||||
wrmsr(0x1b,msr);
|
||||
}
|
||||
apic_id = *((volatile unsigned long *)(APIC_DEFAULT_BASE+APIC_ID));
|
||||
print_debug("apic_id: ");
|
||||
print_debug_hex32(apic_id>>24);
|
||||
print_debug("\r\n");
|
||||
|
||||
if (bsp) {
|
||||
print_debug("Bootstrap cpu\r\n");
|
||||
} else {
|
||||
print_debug("Application processor\r\n");
|
||||
// asm("hlt"); // move to end before halt should notify BSP
|
||||
// if you start AP in coherent.c you can just stop it here
|
||||
}
|
||||
|
||||
return bsp;
|
||||
}
|
||||
|
||||
static int cpu_init_detected(void)
|
||||
{
|
||||
unsigned long dcl;
|
||||
int cpu_init;
|
||||
|
||||
unsigned long htic;
|
||||
|
||||
htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
|
||||
#if 0
|
||||
print_debug("htic: ");
|
||||
print_debug_hex32(htic);
|
||||
print_debug("\r\n");
|
||||
|
||||
if (!(htic & HTIC_ColdR_Detect)) {
|
||||
print_debug("Cold Reset.\r\n");
|
||||
}
|
||||
if ((htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect)) {
|
||||
print_debug("BIOS generated Reset.\r\n");
|
||||
}
|
||||
if (htic & HTIC_INIT_Detect) {
|
||||
print_debug("Init event.\r\n");
|
||||
}
|
||||
#endif
|
||||
cpu_init = (htic & HTIC_INIT_Detect);
|
||||
if (cpu_init) {
|
||||
print_debug("CPU INIT Detected.\r\n");
|
||||
}
|
||||
return cpu_init;
|
||||
}
|
||||
/*
|
||||
static void print_debug_pci_dev(unsigned dev)
|
||||
{
|
||||
print_debug("PCI: ");
|
||||
print_debug_hex8((dev >> 16) & 0xff);
|
||||
print_debug_char(':');
|
||||
print_debug_hex8((dev >> 11) & 0x1f);
|
||||
print_debug_char('.');
|
||||
print_debug_hex8((dev >> 8) & 7);
|
||||
}
|
||||
|
||||
|
||||
static void print_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
uint32_t id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
print_debug_pci_dev(dev);
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
*/
|
||||
/*
|
||||
static void dump_pci_device(unsigned dev)
|
||||
{
|
||||
int i;
|
||||
print_debug_pci_dev(dev);
|
||||
print_debug("\r\n");
|
||||
|
||||
for(i = 0; i <= 255; i++) {
|
||||
unsigned char val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
print_debug_hex8(i);
|
||||
print_debug_char(':');
|
||||
}
|
||||
val = pci_read_config8(dev, i);
|
||||
print_debug_char(' ');
|
||||
print_debug_hex8(val);
|
||||
if ((i & 0x0f) == 0x0f) {
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
static void dump_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
uint32_t id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
dump_pci_device(dev);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void dump_spd_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
int i;
|
||||
print_debug("\r\n");
|
||||
for(i = 0; i < 4; i++) {
|
||||
unsigned device;
|
||||
device = ctrl->channel0[i];
|
||||
if (device) {
|
||||
int j;
|
||||
print_debug("dimm: ");
|
||||
print_debug_hex8(i);
|
||||
print_debug(".0: ");
|
||||
print_debug_hex8(device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
|
||||
unsigned char byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
print_debug("\r\n");
|
||||
print_debug_hex8(j);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
print_debug("bad device\r\n");
|
||||
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\r\n");
|
||||
}
|
||||
device = ctrl->channel1[i];
|
||||
if (device) {
|
||||
int j;
|
||||
print_debug("dimm: ");
|
||||
print_debug_hex8(i);
|
||||
print_debug(".1: ");
|
||||
print_debug_hex8(device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
|
||||
unsigned char byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
print_debug("\r\n");
|
||||
print_debug_hex8(j);
|
||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
|
||||
if (status < 0) {
|
||||
print_debug("bad device\r\n");
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
static void main(void)
|
||||
{
|
||||
static const struct mem_controller cpu0 = {
|
||||
.f0 = PCI_DEV(0, 0x18, 0),
|
||||
.f1 = PCI_DEV(0, 0x18, 1),
|
||||
.f2 = PCI_DEV(0, 0x18, 2),
|
||||
.f3 = PCI_DEV(0, 0x18, 3),
|
||||
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
|
||||
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
|
||||
};
|
||||
static const struct mem_controller cpu1 = {
|
||||
.f0 = PCI_DEV(0, 0x19, 0),
|
||||
.f1 = PCI_DEV(0, 0x19, 1),
|
||||
.f2 = PCI_DEV(0, 0x19, 2),
|
||||
.f3 = PCI_DEV(0, 0x19, 3),
|
||||
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
|
||||
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
|
||||
};
|
||||
|
||||
// device_t dev;
|
||||
// unsigned where;
|
||||
unsigned long reg;
|
||||
// dev = PCI_ADDR(0, 0x19, 0, 0x6C) & ~0xff;
|
||||
// where = PCI_ADDR(0, 0x19, 0, 0x6C) & 0xff;
|
||||
#if 0
|
||||
init_apic_timer();
|
||||
#endif
|
||||
|
||||
uart_init();
|
||||
console_init();
|
||||
if (boot_cpu() && !cpu_init_detected()) {
|
||||
setup_default_resource_map();
|
||||
setup_coherent_ht_domain();
|
||||
enumerate_ht_chain();
|
||||
// print_pci_devices();
|
||||
enable_smbus();
|
||||
// sdram_initialize();
|
||||
// dump_spd_registers(&cpu0);
|
||||
sdram_initialize(&cpu0);
|
||||
// dump_spd_registers(&cpu1);
|
||||
// sdram_initialize(&cpu1);
|
||||
|
||||
// dump_pci_device(PCI_DEV(0, 0x18, 2));
|
||||
#if 0
|
||||
ram_fill( 0x00100000, 0x00180000);
|
||||
ram_verify(0x00100000, 0x00180000);
|
||||
#endif
|
||||
//#ifdef MEMORY_1024MB
|
||||
// ram_fill( 0x00000000, 0x00001000);
|
||||
// ram_verify(0x00000000, 0x00001000);
|
||||
//#endif
|
||||
//#ifdef MEMROY_512MB
|
||||
// ram_fill( 0x00000000, 0x01ffffff);
|
||||
// ram_verify(0x00000000, 0x01ffffff);
|
||||
//#endif
|
||||
/* Check the first 512M */
|
||||
/* msr_t msr;
|
||||
msr = rdmsr(TOP_MEM);
|
||||
print_debug("TOP_MEM: ");
|
||||
print_debug_hex32(msr.hi);
|
||||
print_debug_hex32(msr.lo);
|
||||
print_debug("\r\n");
|
||||
ram_check(0x00000000, msr.lo);
|
||||
*/
|
||||
/*
|
||||
reg = *((volatile unsigned long *)(APIC_DEFAULT_BASE+APIC_ID));
|
||||
print_debug("bootstrap cpu apic_id: ");
|
||||
print_debug_hex32(reg>>24);
|
||||
print_debug("\r\n");
|
||||
*/
|
||||
|
||||
// Start AP now
|
||||
reg = pci_read_config32(PCI_DEV(0, 0x19, 0), 0x6C);
|
||||
reg &= 0xffffff8c;
|
||||
reg |= 0x00000070;
|
||||
pci_write_config32(PCI_DEV(0, 0x19, 0), 0x6C, reg); //start AP
|
||||
for(;;) {
|
||||
reg = pci_read_config32(PCI_DEV(0, 0x19, 0), 0x6C);
|
||||
if((reg & (1<<4))==0) break; // wait until AP stop
|
||||
}
|
||||
reg |= 1<<4;
|
||||
pci_write_config32(PCI_DEV(0, 0x19, 0), 0x6C, reg);
|
||||
|
||||
}
|
||||
else {
|
||||
// Need to init second cpu's APIC id
|
||||
// It's AP
|
||||
|
||||
// apic_write(APIC_ID,(1<<24));
|
||||
reg = *((volatile unsigned long *)(APIC_DEFAULT_BASE+APIC_ID));
|
||||
/* print_debug("applicaton cpu apic_id: ");
|
||||
print_debug_hex32(reg>>24);
|
||||
print_debug("\r\n");
|
||||
if((reg>>24)==7){ // FIXME: Need to read NodeID at first.
|
||||
*((volatile unsigned long *)(APIC_DEFAULT_BASE+APIC_ID))=1<<24;
|
||||
}*/
|
||||
if((reg>>24)!=0) {
|
||||
// before hlt clear the ColdResetbit
|
||||
|
||||
//notify BSP that AP is stopped
|
||||
reg = pci_read_config32(PCI_DEV(0, 0x19, 0), 0x6C);
|
||||
reg &= ~(1<<4);
|
||||
pci_write_config32(PCI_DEV(0, 0x19, 0), 0x6C, reg);
|
||||
|
||||
asm("hlt");
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
74
src/mainboard/tyan/s2880/cmos.layout
Normal file
74
src/mainboard/tyan/s2880/cmos.layout
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
1008 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 1007 1008
|
||||
|
||||
|
||||
26
src/mainboard/tyan/s2880/failover.c
Normal file
26
src/mainboard/tyan/s2880/failover.c
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
#define ASSEMBLY 1
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "arch/romcc_io.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
|
||||
|
||||
|
||||
static void main(void)
|
||||
{
|
||||
if (do_normal_boot()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
|
||||
/* Allow the HT devices to be found */
|
||||
enumerate_ht_chain();
|
||||
|
||||
/* Setup the 8111 */
|
||||
amd8111_enable_rom();
|
||||
|
||||
/* Jump to the normal image */
|
||||
asm("jmp __normal_image");
|
||||
}
|
||||
}
|
||||
37
src/mainboard/tyan/s2880/irq_tables.c
Normal file
37
src/mainboard/tyan/s2880/irq_tables.c
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
|
||||
|
||||
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*13, /* there can be total 13 devices on the bus */
|
||||
0, /* Where the interrupt router lies (bus) */
|
||||
0x3b, /* Where the interrupt router lies (dev) */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1022, /* Vendor */
|
||||
0x746b, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xe8, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
{0,0x38, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x3,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x2,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
||||
{0x2,0x30, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
|
||||
{0x2,0x20, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
|
||||
{0x1,0x40, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
||||
{0x1,0x38, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
|
||||
{0x3,0x8, {{0x1, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x3,0x30, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x3,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
||||
{0x1,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x3,0x28, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x1,0x50, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
}
|
||||
};
|
||||
120
src/mainboard/tyan/s2880/mainboard.c
Normal file
120
src/mainboard/tyan/s2880/mainboard.c
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <part/mainboard.h>
|
||||
//#include "lsi_scsi.c"
|
||||
unsigned long initial_apicid[MAX_CPUS] =
|
||||
{
|
||||
0,1
|
||||
};
|
||||
/*
|
||||
static void fixup_lsi_53c1030(struct device *pdev)
|
||||
{
|
||||
// uint8_t byte;
|
||||
uint16_t word;
|
||||
|
||||
byte = 1;
|
||||
pci_write_config8(pdev, 0xff, byte);
|
||||
// Set the device id
|
||||
// pci_write_config_word(pdev, PCI_DEVICE_ID, PCI_DEVICE_ID_LSILOGIC_53C1030);
|
||||
// Set the subsytem vendor id
|
||||
// pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_TYAN);
|
||||
word = 0x10f1;
|
||||
pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, word);
|
||||
// Set the subsytem id
|
||||
word = 0x2880;
|
||||
pci_write_config16(pdev, PCI_SUBSYSTEM_ID, word);
|
||||
// Disable writes to the device id
|
||||
byte = 0;
|
||||
pci_write_config8(pdev, 0xff, byte);
|
||||
|
||||
// lsi_scsi_init(pdev);
|
||||
|
||||
}
|
||||
//extern static void lsi_scsi_init(struct device *dev);
|
||||
static void print_pci_regs(struct device *dev)
|
||||
{
|
||||
uint8_t byte;
|
||||
int i;
|
||||
|
||||
for(i=0;i<256;i++) {
|
||||
byte = pci_read_config8(dev, i);
|
||||
|
||||
if((i%16)==0) printk_info("\n %02x:",i);
|
||||
printk_debug(" %02x ",byte);
|
||||
}
|
||||
printk_debug("\r\n");
|
||||
|
||||
// pci_write_config8(dev, 0x4, byte);
|
||||
|
||||
}
|
||||
*/
|
||||
static void onboard_scsi_fixup(void)
|
||||
{
|
||||
struct device *dev;
|
||||
/*
|
||||
// Set the scsi device id's
|
||||
printk_debug("%2d:%2d:%2d\n",0,1,0);
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1, 0));
|
||||
if (dev) {
|
||||
}
|
||||
// Set the scsi device id's
|
||||
printk_debug("%2d:%2d:%2d\n",0,2,0);
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x2, 0));
|
||||
if (dev) {
|
||||
print_pci_regs(dev);
|
||||
}
|
||||
|
||||
// Set the scsi device id's
|
||||
printk_debug("%2d:%2d:%2d\n",1,0xa,0);
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0xa, 0));
|
||||
if (dev) {
|
||||
print_pci_regs(dev);
|
||||
}
|
||||
// Set the scsi device id's
|
||||
printk_debug("%2d:%2d:%2d\n",1,0xa,1);
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0xa, 1));
|
||||
if (dev) {
|
||||
print_pci_regs(dev);
|
||||
}
|
||||
printk_debug("%2d:%2d:%2d\n",1,9,0);
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x9, 0));
|
||||
if (dev) {
|
||||
print_pci_regs(dev);
|
||||
}
|
||||
// Set the scsi device id's
|
||||
printk_debug("%2d:%2d:%2d\n",1,9,1);
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x9, 1));
|
||||
if (dev) {
|
||||
print_pci_regs(dev);
|
||||
}
|
||||
*/
|
||||
|
||||
/*
|
||||
dev = dev_find_device(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_53C1030,0);
|
||||
if(!dev) {
|
||||
printk_info("LSI_SCSI_FW_FIXUP: No Device Found!");
|
||||
return;
|
||||
}
|
||||
|
||||
lsi_scsi_init(dev);
|
||||
*/
|
||||
}
|
||||
|
||||
void mainboard_fixup(void)
|
||||
{
|
||||
printk_debug("Enter mainboard_fixup\r\n");
|
||||
// onboard_device_fixup
|
||||
onboard_scsi_fixup();
|
||||
printk_debug("mainboard fixup done\r\n");
|
||||
|
||||
}
|
||||
void final_mainboard_fixup(void)
|
||||
{
|
||||
#if 0
|
||||
enable_ide_devices();
|
||||
#endif
|
||||
}
|
||||
|
||||
99
src/mainboard/tyan/s2880/mptable.c
Normal file
99
src/mainboard/tyan/s2880/mptable.c
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
void *smp_write_config_table(void *v, unsigned long * processor_map)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "TYAN ";
|
||||
static const char productid[12] = "S2880 ";
|
||||
struct mp_config_table *mc;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc, processor_map);
|
||||
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
smp_write_bus(mc, 0, "PCI ");
|
||||
smp_write_bus(mc, 1, "PCI ");
|
||||
smp_write_bus(mc, 2, "PCI ");
|
||||
smp_write_bus(mc, 3, "PCI ");
|
||||
smp_write_bus(mc, 4, "ISA ");
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
uint32_t base;
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1,1));
|
||||
if (dev) {
|
||||
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 3, 0x11, base);
|
||||
}
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x2,1));
|
||||
if (dev) {
|
||||
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 4, 0x11, base);
|
||||
}
|
||||
}
|
||||
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||
*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x0, 0x2, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x1, 0x2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x0, 0x2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x3, 0x2, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x4, 0x2, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x6, 0x2, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x7, 0x2, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x8, 0x2, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xc, 0x2, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xd, 0x2, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xe, 0x2, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xf, 0x2, 0xf);
|
||||
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x3, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x18, 0x2, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x14, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x24, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x25, 0x3, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x28, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x29, 0x3, 0x1);
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v, processor_map);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue