- Updates for the supermicro p4dc6 motherboard

- Code to initialize sdram from C on the l440gx
- cache as ram code fro the p6 it works except conflict misses occur
  with addresses that are not cached so writing to ram does not work.
  Which makes it to brittle to count on.
- Initial implementation of a fallback booting scheme where we can
  have two copies of linuxbios in rom at once.
- Movement of 32 bit entry code from entry16.inc to entry32.inc
- Update of all config files so they now also include entry32.inc
- Fix for start_stop.c & entry16.inc so I can fairly arbitrarily relocate
  the 16bit entry code in SMP.
- A small number of fixes for warnings

src/include/cpu/i786/multiplier.h

@@ -0,0 +1,55 @@
+
+/* 
+ ** NMI A20M IGNNE INTR
+ * X8  H H H H
+ * X9  H H H L projected
+ * X10 H H L H
+ * X11 H H L L
+ * X12 H L H H
+ * X13 H L H L
+ * X14 H L L H
+ * X15 H L L L 
+ * X16 L H H H
+ * X17 L H H L
+ * X18 L H L H
+ * X19 L H L L
+ * X20 L L H H
+ * X21 L L H L  projected
+ * X22 L L L H  projected
+ * X23 L L L L  projected
+ *
+ ** NMI INTR IGNNE A20M 
+ * X8  H H H H
+ * X9  H L H H projected
+ * X10 H H L H
+ * X11 H L L H
+ * X12 H H H L
+ * X13 H L H L
+ * X14 H H L L
+ * X15 H L L L 
+ * X16 L H H H
+ * X17 L L H H
+ * X18 L H L H
+ * X19 L L L H
+ * X20 L H H L
+ * X21 L L H L projected
+ * X22 L H L L projected
+ * X23 L L L L projected
+ */
+
+#define XEON_X8	 0xf
+#define XEON_X9  0xb  /* projected */
+#define XEON_X10 0xd
+#define XEON_X11 0x9
+#define XEON_X12 0xe
+#define XEON_X13 0xa
+#define XEON_X14 0xc
+#define XEON_X15 0x8
+#define XEON_X16 0x7
+#define XEON_X17 0x3
+#define XEON_X18 0x5
+#define XEON_X19 0x1
+#define XEON_X20 0x6
+#define XEON_X21 0x2  /* projected */
+#define XEON_X22 0x4  /* projected */
+#define XEON_X23 0x0  /* projected */

src/include/cpu/p6/mtrr.h

@@ -33,6 +33,7 @@
 
 #if !defined(ASSEMBLY)
 
+void set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type);
 #if defined(INTEL_PPRO_MTRR) 
 void setup_mtrrs(unsigned long ramsizeK);
 #endif

src/include/loglevel.h

@@ -7,6 +7,10 @@
 #define MAXIMUM_CONSOLE_LOGLEVEL 8
 #endif
 
+#ifndef DEFAULT_CONSOLE_LOGLEVEL
+#define DEFAULT_CONSOLE_LOGLEVEL 8 /* anything MORE serious than BIOS_SPEW */
+#endif
+
 #if (DEFAULT_CONSOLE_LOGLEVEL <= MAXIMUM_CONSOLE_LOGLEVEL)
 #define ASM_CONSOLE_LOGLEVEL DEFAULT_CONSOLE_LOGLEVEL
 #else

src/include/part/fallback_boot.h

@@ -0,0 +1,16 @@
+#ifndef PART_FALLBACK_BOOT_H
+#define PART_FALLBACK_BOOT_H
+
+#if !defined(ASSEMBLY)
+
+#if USE_FALLBACK_BOOT
+void boot_successful(void);
+#  else
+#    define boot_successful()
+#endif
+
+#endif /* ASSEMBLY */
+
+#define RTC_BOOT_BYTE	48
+
+#endif /* PART_FALLBACK_BOOT_H */

src/include/pc80/isa_dma.h

@@ -0,0 +1,6 @@
+#ifndef PC80_ISA_DMA_H
+#define PC80_ISA_DMA_H
+
+void isa_dma_init(void);
+
+#endif /* PC80_ISA_DMA_H */

src/include/pc80/mc146818rtc.h

@@ -0,0 +1,95 @@
+#ifndef PC80_MC146818RTC_H
+#define PC80_MC146818RTC_H
+
+#ifndef RTC_BASE_PORT
+#define RTC_BASE_PORT 0x70
+#endif
+
+#define RTC_PORT(x)	(RTC_BASE_PORT + (x))
+
+/* On PCs, the checksum is built only over bytes 16..45 */
+#define PC_CKS_RANGE_START	16
+#define PC_CKS_RANGE_END	45
+#define PC_CKS_LOC		46
+
+
+/* control registers - Moto names
+ */
+#define RTC_REG_A		10
+#define RTC_REG_B		11
+#define RTC_REG_C		12
+#define RTC_REG_D		13
+
+
+/**********************************************************************
+ * register details
+ **********************************************************************/
+#define RTC_FREQ_SELECT	RTC_REG_A
+
+/* update-in-progress  - set to "1" 244 microsecs before RTC goes off the bus,
+ * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
+ * totalling to a max high interval of 2.228 ms.
+ */
+# define RTC_UIP		0x80
+# define RTC_DIV_CTL		0x70
+   /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
+#  define RTC_REF_CLCK_4MHZ	0x00
+#  define RTC_REF_CLCK_1MHZ	0x10
+#  define RTC_REF_CLCK_32KHZ	0x20
+   /* 2 values for divider stage reset, others for "testing purposes only" */
+#  define RTC_DIV_RESET1	0x60
+#  define RTC_DIV_RESET2	0x70
+  /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
+# define RTC_RATE_SELECT 	0x0F
+#  define RTC_RATE_NONE		0x00
+#  define RTC_RATE_32786HZ	0x01
+#  define RTC_RATE_16384HZ	0x02
+#  define RTC_RATE_8192HZ	0x03
+#  define RTC_RATE_4096HZ	0x04
+#  define RTC_RATE_2048HZ	0x05
+#  define RTC_RATE_1024HZ	0x06
+#  define RTC_RATE_512HZ	0x07
+#  define RTC_RATE_256HZ	0x08
+#  define RTC_RATE_128HZ	0x09
+#  define RTC_RATE_64HZ		0x0a
+#  define RTC_RATE_32HZ		0x0b
+#  define RTC_RATE_16HZ		0x0c
+#  define RTC_RATE_8HZ		0x0d
+#  define RTC_RATE_4HZ		0x0e
+#  define RTC_RATE_2HZ		0x0f
+
+/**********************************************************************/
+#define RTC_CONTROL	RTC_REG_B
+# define RTC_SET 0x80		/* disable updates for clock setting */
+# define RTC_PIE 0x40		/* periodic interrupt enable */
+# define RTC_AIE 0x20		/* alarm interrupt enable */
+# define RTC_UIE 0x10		/* update-finished interrupt enable */
+# define RTC_SQWE 0x08		/* enable square-wave output */
+# define RTC_DM_BINARY 0x04	/* all time/date values are BCD if clear */
+# define RTC_24H 0x02		/* 24 hour mode - else hours bit 7 means pm */
+# define RTC_DST_EN 0x01	/* auto switch DST - works f. USA only */
+
+/**********************************************************************/
+#define RTC_INTR_FLAGS	RTC_REG_C
+/* caution - cleared by read */
+# define RTC_IRQF 0x80		/* any of the following 3 is active */
+# define RTC_PF 0x40
+# define RTC_AF 0x20
+# define RTC_UF 0x10
+
+/**********************************************************************/
+#define RTC_VALID	RTC_REG_D
+# define RTC_VRT 0x80		/* valid RAM and time */
+/**********************************************************************/
+
+
+/* On PCs, the checksum is built only over bytes 16..45 */
+#define PC_CKS_RANGE_START	16
+#define PC_CKS_RANGE_END	45
+#define PC_CKS_LOC		46
+
+#if !defined(ASSEMBLY)
+void rtc_init(int invalid);
+#endif
+
+#endif /*  PC80_MC146818RTC_H */

src/include/ramtest.h

@@ -0,0 +1,8 @@
+#ifndef RAMTEST_H
+#define RAMTEST_H
+
+void ram_fill(unsigned long start, unsigned long stop);
+int ram_verify(unsigned long start, unsigned long stop, int max_errors);
+int ramcheck(unsigned long start, unsigned long stop, int max_errors);
+
+#endif /* RAMTEST_H */

src/include/sdram.h

@@ -0,0 +1,23 @@
+#ifndef SDRAM_H
+#define SDRAM_H 
+
+void sdram_no_memory(void);
+void sdram_initialize(void);
+void sdram_set_registers(void);
+void sdram_set_spd_registers(void);
+void sdram_enable(void);
+void sdram_first_normal_reference(void);
+void sdram_enable_refresh(void);
+void sdram_special_finishup(void);
+
+void sdram_set_command_noop(void);
+void sdram_set_command_precharge(void);
+void sdram_set_command_cbr(void);
+void sdram_set_command_none(void);
+void sdram_assert_command(void);
+void sdram_set_mode_register(void);
+
+void sdram_initialize_ecc(void);
+unsigned long sdram_get_ecc_size_bytes(void);
+
+#endif /* SDRAM_H */

src/include/smbus.h

@@ -0,0 +1,8 @@
+#ifndef SMBUS_H
+#define SMBUS_H
+
+void smbus_enable(void);
+void smbus_setup(void);
+int smbus_read_byte(unsigned device, unsigned address, unsigned char *result);
+
+#endif /* SMBUS_H */

src/include/southbridge/intel/82801.h

@@ -1,5 +1,13 @@
+#ifndef SOUTHBRIDGE_INTEL_82801_H
+#define SOUTHBRIDGE_INTEL_82801_H
 
 void ich2_enable_serial_irqs(void);
 void ich2_lpc_route_dma(unsigned char mask);
 void ich2_enable_ioapic(void);
 void ich2_enable_ide(int enable_a, int enable_b);
+void ich2_hard_reset(void);
+void ich2_set_cpu_multiplier(unsigned);
+void ich2_rtc_init(void);
+void ich2_power_after_power_fail(int on);
+
+#endif /* SOUTHBRIDGE_INTEL_82801_H */

src/include/superio/generic.h

@@ -0,0 +1,15 @@
+#ifndef SUPERIO_GENERIC_H
+#define SUPERIO_GENERIC_H
+
+void pnp_write_config(unsigned char port, unsigned char value, unsigned char reg);
+unsigned char pnp_read_config(unsigned char port, unsigned char reg);
+void pnp_set_logical_device(unsigned char port, int device);
+void pnp_set_enable(unsigned char port, int enable);
+int pnp_read_enable(unsigned char port);
+void pnp_set_iobase0(unsigned char port, unsigned iobase);
+void pnp_set_iobase1(unsigned char port, unsigned iobase);
+void pnp_set_irq0(unsigned char port, unsigned irq);
+void pnp_set_irq1(unsigned char port, unsigned irq);
+void pnp_set_drq(unsigned char port, unsigned drq);
+
+#endif /* SUPERIO_GENERIC_H */

src/include/superio/w83627hf.h

@@ -0,0 +1,59 @@
+#ifndef SUPERIO_W83627HF_H
+#define SUPERIO_W83627HF_H
+
+/* The base address is 0x2e,0x4e depending on config bytes */
+#ifndef SIO_BASE
+#define SIO_BASE 0x2e
+#endif
+
+#define SIO_SYSTEM_CLK_INPUT_48MHZ	(1<<6)
+#define SIO_SYSTEM_CLK_INPUT_24MHZ	(0<<6)
+
+#if defined(SIO_SYSTEM_CLK_INPUT)
+#if (SIO_SYSTEM_CLK_INPUT != SIO_SYSTEM_CLK_INPUT_48MHZ) &&  (SIO_SYSTEM_CLK_INPUT != SIO_SYSTEM_CLK_INPUT_24MHZ) 
+#error BAD SIO_SYSTEM_CLK_INPUT_PARAMETER
+#endif
+#endif
+
+#define FLOPPY_DEVICE 0
+#define PARALLEL_DEVICE 1
+#define COM1_DEVICE 2
+#define COM2_DEVICE 3
+#define KBC_DEVICE  5
+#define CIR_DEVICE  6
+#define GAME_PORT_DEVICE 7
+#define GPIO_PORT2_DEVICE 8
+#define GPIO_PORT3_DEVICE 9
+#define ACPI_DEVICE 0xa
+#define HW_MONITOR_DEVICE 0xb
+
+
+#define FLOPPY_DEFAULT_IOBASE	0x3f0
+#define FLOPPY_DEFAULT_IRQ	6
+#define FLOPPY_DEFAULT_DRQ	2
+#define PARALLEL_DEFAULT_IOBASE	0x378
+#define PARALLEL_DEFAULT_IRQ	7
+#define PARALLEL_DEFAULT_DRQ	4 /* No dma */
+#define COM1_DEFAULT_IOBASE	0x3f8
+#define COM1_DEFAULT_IRQ	4
+#define COM1_DEFAULT_BAUD	115200
+#define COM2_DEFAULT_IOBASE	0x2f8
+#define COM2_DEFAULT_IRQ	3
+#define COM2_DEFAULT_BAUD	115200
+#define KBC_DEFAULT_IOBASE0	0x60
+#define KBC_DEFAULT_IOBASE1	0x64
+#define KBC_DEFAULT_IRQ0	0x1
+#define KBC_DEFAULT_IRQ1	0xc
+
+#if !defined(ASSEMBLY)
+void w83627hf_enter_pnp(unsigned char port);
+void w83627hf_exit_pnp(unsigned char port);
+
+#define POWER_OFF  0
+#define POWER_ON   1
+#define POWER_PREV 2
+
+void w832627hf_power_after_power_fail(int state);
+#endif
+
+#endif /* SUPERIO_W83627HF_H */