- Updates for the supermicro p4dc6 motherboard
- Code to initialize sdram from C on the l440gx - cache as ram code fro the p6 it works except conflict misses occur with addresses that are not cached so writing to ram does not work. Which makes it to brittle to count on. - Initial implementation of a fallback booting scheme where we can have two copies of linuxbios in rom at once. - Movement of 32 bit entry code from entry16.inc to entry32.inc - Update of all config files so they now also include entry32.inc - Fix for start_stop.c & entry16.inc so I can fairly arbitrarily relocate the 16bit entry code in SMP. - A small number of fixes for warnings
This commit is contained in:
Eric W. Biederman
parent
0ddd8a6f16
commit
2beb0a1bcc
97 changed files with 2517 additions and 291 deletions
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@ -25,8 +25,6 @@ it with the version available from LANL.
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* protected mode.
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*/
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#include <arch/cache_ram.h>
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.text
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.code16
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.globl EXT(_start)
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@ -41,8 +39,8 @@ EXT(_start):
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/* any further code. Even though paging is disabled we could still get*/
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/*false address translations due to the TLB if we didn't invalidate it.*/
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/**/
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xor %eax, %eax
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mov %eax, %cr3 /* Invalidate TLB*/
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xorl %eax, %eax
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movl %eax, %cr3 /* Invalidate TLB*/
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/* invalidate the cache */
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invd
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@ -66,18 +64,28 @@ EXT(_start):
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* So while this code is relocateable it isn't arbitrarily
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* relocatable.
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*
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* In particular this code can be run with the base address of
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* the code segment at either 0xffff0000 or 0xf0000.
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* The first is what is initiallly loaded when the processor
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* powers on. The second is normal real mode segment 0xf000.
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* The criteria for relocation have been relaxed to their
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* utmost, so that we can use the same code for both
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* our initial entry point and startup of the second cpu.
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* The code assumes when executing at _start that:
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* (((cs & 0xfff) == 0) and (ip == _start & 0xffff))
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* or
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* ((cs == anything) and (ip == 0)).
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*
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* At this point all the linker script does when calculating
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* gdtptr_offset is return the low 16 bits so your segment
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* must be 64K aligned. So it wouldn't be too much work
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* to support other segments, I just don't see the point
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* right now.
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* The restrictions in reset16.inc mean that _start initially
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* must be loaded at or above 0xffff0000 or below 0x100000.
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*
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* The linker scripts computs gdtptr16_offset by simply returning
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* the low 16 bits. This means that the intial segment used
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* when start is called must be 64K aligned. This should not
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* restrict the address as the ip address can be anything.
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*/
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data32 lgdt %cs:EXT(gdtptr_offset)
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movw %cs, %ax
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shlw $4, %ax
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movw $EXT(gdtptr16_offset), %bx
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subw %ax, %bx
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data32 lgdt %cs:(%bx)
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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@ -85,62 +93,19 @@ EXT(_start):
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movl %eax, %cr0
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/* Now that we are in protected mode jump to a 32 bit code segment. */
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data32 ljmp $0x10, $_protected_start
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data32 ljmp $0x10, $__protected_start
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/** This gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
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/** The gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
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* at 0x18; these are Linux-compatible.
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*/
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/** GDT. we have modified this from the original freebios to make it
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* compatible with linux. This puts text at seg 0x10 and data at 0x18
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*/
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.align 4
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.globl EXT(gdtptr)
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EXT(gdtptr):
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.globl EXT(gdtptr16)
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EXT(gdtptr16):
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.word 4*8-1
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.long gdt /* we know the offset */
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.globl EXT(_estart)
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EXT(_estart):
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gdt:
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.word 0x0000, 0x0000 /* dummy */
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.byte 0x00, 0x00, 0x00, 0x00
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.word 0xffff, (CACHE_RAM_SEG_BASE & 0xffff) /* flat offset data segment */
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.byte ((CACHE_RAM_SEG_BASE >> 16)& 0xff), 0x93, 0xcf
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.byte ((CACHE_RAM_SEG_BASE >> 24) & 0xff)
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.word 0xffff, 0x0000 /* flat code segment */
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.byte 0x00, 0x9b, 0xcf, 0x00
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.word 0xffff, 0x0000 /* flat data segment */
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.byte 0x00, 0x93, 0xcf, 0x00
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/*
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* When we come here we are in protected mode. We expand
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* the stack and copies the data segment from ROM to the
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* memory.
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*
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* After that, we call the chipset bootstrap routine that
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* does what is left of the chipset initialization.
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*
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* NOTE aligned to 4 so that we are sure that the prefetch
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* cache will be reloaded.
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*/
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.align 4
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_protected_start:
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.code32
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intel_chip_post_macro(0x10) /* post 10 */
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movw $0x18, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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@ -1,2 +1,2 @@
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gdtptr_offset = gdtptr & 0xffff;
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gdtptr16_offset = gdtptr16 & 0xffff;
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_start_offset = _start & 0xffff;
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@ -1,5 +1,63 @@
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/* For starting linuxBIOS in protected mode */
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/* For starting linuxBIOS in protected mode */
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#include <arch/cache_ram.h>
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.text
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.align 4
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.code32
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/** This gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
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* at 0x18; these are Linux-compatible.
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*/
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/** GDT. we have modified this from the original freebios to make it
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* compatible with linux. This puts text at seg 0x10 and data at 0x18
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*/
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.align 4
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.globl EXT(gdtptr)
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EXT(gdtptr):
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.word 4*8-1
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.long gdt /* we know the offset */
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gdt:
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.word 0x0000, 0x0000 /* dummy */
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.byte 0x00, 0x00, 0x00, 0x00
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.word 0xffff, (CACHE_RAM_SEG_BASE & 0xffff) /* flat offset data segment */
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.byte ((CACHE_RAM_SEG_BASE >> 16)& 0xff), 0x93, 0xcf
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.byte ((CACHE_RAM_SEG_BASE >> 24) & 0xff)
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.word 0xffff, 0x0000 /* flat code segment */
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.byte 0x00, 0x9b, 0xcf, 0x00
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.word 0xffff, 0x0000 /* flat data segment */
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.byte 0x00, 0x93, 0xcf, 0x00
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/*
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* When we come here we are in protected mode. We expand
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* the stack and copies the data segment from ROM to the
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* memory.
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*
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* After that, we call the chipset bootstrap routine that
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* does what is left of the chipset initialization.
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*
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* NOTE aligned to 4 so that we are sure that the prefetch
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* cache will be reloaded.
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*/
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.align 4
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.globl EXT(protected_start)
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EXT(protected_start):
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lgdt %cs:gdtptr
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ljmp $0x10, $__protected_start
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__protected_start:
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intel_chip_post_macro(0x10) /* post 10 */
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movw $0x18, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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@ -20,5 +20,8 @@ EXT(reset_vector):
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#error _ROMBASE is an unsupported value
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#endif
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. = 0x8;
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.code32
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jmp EXT(protected_start)
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.previous
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10
src/cpu/i386/reset32.inc
Normal file
10
src/cpu/i386/reset32.inc
Normal file
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@ -0,0 +1,10 @@
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.section ".reset"
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.code16
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.globl EXT(reset_vector)
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EXT(reset_vector):
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. = 0x8;
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.code32
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jmp EXT(protected_start)
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.previous
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14
src/cpu/i386/reset32.lds
Normal file
14
src/cpu/i386/reset32.lds
Normal file
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@ -0,0 +1,14 @@
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/*
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* _ROMTOP : The top of the rom used where we
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* need to put the reset vector.
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*/
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SECTIONS {
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_ROMTOP = _ROMBASE + ROM_IMAGE_SIZE - 0x10;
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. = _ROMTOP;
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.reset (.): {
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*(.reset)
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. = 15 ;
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BYTE(0x00);
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}
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}
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@ -44,4 +44,4 @@
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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#endif
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#endif
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40
src/cpu/p6/cache_ram_fini.inc
Normal file
40
src/cpu/p6/cache_ram_fini.inc
Normal file
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@ -0,0 +1,40 @@
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#if defined(CACHE_RAM_BASE) && defined(CACHE_RAM_SIZE)
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/* Note: We cannot be running from simulated ram in
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* this code. If we are evil things will happen.
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*/
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/* Disable the cache */
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movl %cr0, %eax
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orl $0x40000000, %eax
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movl %eax, %cr0
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/* Flush everything that is left in the cache,
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* We don't want random writes to memory to occur later on.
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*/
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invd
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/* Disable the cache ram mtrr */
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movl $0x204, %ecx
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xorl %eax, %eax
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xorl %edx, %edx
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wrmsr
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movl $0x205, %ecx
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xorl %eax, %eax
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xorl %edx, %edx
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wrmsr
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/* Reenable the cache now that the mtrr is cleared */
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movl %cr0, %eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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/* Reload the normal data segments */
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movw $0x18, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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#endif
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48
src/cpu/p6/cache_ram_init.inc
Normal file
48
src/cpu/p6/cache_ram_init.inc
Normal file
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@ -0,0 +1,48 @@
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#if defined(CACHE_RAM_BASE) && defined(CACHE_RAM_SIZE)
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/* Disable the cache while we set up the cache ram MTRR */
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movl %cr0, %eax
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orl $0x40000000, %eax
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movl %eax, %cr0
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/* Set up an mtrr in write-back mode over some arbitrary
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* location. As long as we do not get a capacity miss,
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* or a multiprocessor conflict miss this should allow us to
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* function as if we have memory even when it hasn't been
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* enabled yet.
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*/
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movl $0x204, %ecx /* mtrr[0] physical base register */
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xorl %edx, %edx
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movl $(CACHE_RAM_BASE | 0x006), %eax
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wrmsr
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movl $0x205, %ecx /* mtrr[0] physical mask register */
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movl $0x0000000f, %edx
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movl $(~(CACHE_RAM_SIZE - 1) | 0x800), %eax
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wrmsr
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/* Reenable the cache now that the mtrr is set up */
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movl %cr0, %eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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/* Force cache ram area into cache
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* Note: Some versions of the P4 don't allocate a cache
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* line on write immediately after a mtrr change, so
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* we make certain we read the address before we write
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* to it.
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*/
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movl $CACHE_RAM_BASE, %esi
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movl $(CACHE_RAM_BASE + CACHE_RAM_SIZE), %edi
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1:
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movl (%esi), %eax
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addl $4, %esi
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movl %eax, -4(%esi)
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cmpl %esi, %edi
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jnz 1b
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/* Load a different set of data segments */
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movw $0x08, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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#endif
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27
src/cpu/p6/cache_ram_start.inc
Normal file
27
src/cpu/p6/cache_ram_start.inc
Normal file
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@ -0,0 +1,27 @@
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#include <arch/cache_ram.h>
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/* copy data segment from FLASH ROM to CACHE */
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movl $(EXT(_ldata) - CACHE_RAM_SEG_BASE), %esi
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movl $EXT(_data), %edi
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movl $(EXT(_eldata) - CACHE_RAM_SEG_BASE), %ecx
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subl %esi, %ecx
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jz 1f /* should not happen */
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rep
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movsb
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1:
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/** clear bss */
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movl $EXT(_bss), %edi
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movl $EXT(_ebss), %ecx
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subl %edi, %ecx
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jz 1f
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xorl %eax, %eax
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rep
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stosb
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1:
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/* set new stack */
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movl $(_stack + STACK_SIZE), %esp
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call cache_ram_start
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@ -225,6 +225,42 @@ static void intel_set_var_mtrr(unsigned int reg, unsigned long base, unsigned lo
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}
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/* setting variable mtrr, comes from linux kernel source */
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void set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type)
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{
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unsigned int tmp;
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if (reg >= 8)
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return;
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// it is recommended that we disable and enable cache when we
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// do this.
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/* Disable cache */
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/* Write back the cache and flush TLB */
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asm volatile (
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"movl %%cr0, %0\n\t"
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"orl $0x40000000, %0\n\t"
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"movl %0, %%cr0\n\t"
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:"=r" (tmp)
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::"memory");
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if (size == 0) {
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/* The invalid bit is kept in the mask, so we simply clear the
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relevant mask register to disable a range. */
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wrmsr (MTRRphysMask_MSR (reg), 0, 0);
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} else {
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/* Bit 32-35 of MTRRphysMask should be set to 1 */
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wrmsr (MTRRphysBase_MSR (reg), base | type, 0);
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wrmsr (MTRRphysMask_MSR (reg), ~(size - 1) | 0x800, 0x0F);
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}
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// turn cache back on.
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asm volatile ("movl %%cr0, %0\n\t"
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"andl $0x9fffffff, %0\n\t"
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"movl %0, %%cr0\n\t":"=r" (tmp)::"memory");
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}
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/* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
|
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static __inline__ unsigned int fms(unsigned int x)
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||||
{
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|
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Loading…
Add table
Add a link
Reference in a new issue