- Updates for the supermicro p4dc6 motherboard

- Code to initialize sdram from C on the l440gx
- cache as ram code fro the p6 it works except conflict misses occur
  with addresses that are not cached so writing to ram does not work.
  Which makes it to brittle to count on.
- Initial implementation of a fallback booting scheme where we can
  have two copies of linuxbios in rom at once.
- Movement of 32 bit entry code from entry16.inc to entry32.inc
- Update of all config files so they now also include entry32.inc
- Fix for start_stop.c & entry16.inc so I can fairly arbitrarily relocate
  the 16bit entry code in SMP.
- A small number of fixes for warnings

src/arch/i386/include/arch/cache_ram.h

@@ -5,9 +5,20 @@
 #define CACHE_RAM_BASE 0
 #endif
 
+#if !defined(ASSEMBLY)
+#define CACHE_RAM_SEG_BASE (((unsigned long)CACHE_RAM_BASE) - ((unsigned long)_RAMBASE))
+#else
 #define CACHE_RAM_SEG_BASE (CACHE_RAM_BASE - _RAMBASE)
+#endif
 
-#define RAM(type, addr) (*((type *)((unsigned char*)((addr) - CACHE_RAM_SEG_BASE))))
-#define RAM_ADDR( addr) ((void *)((addr) - CACHE_RAM_BASE))
+
+
+#if !defined(ASSEMBLY)
+
+#define RAM_ADDR( addr) ((void *)(((unsigned char *)(addr)) - CACHE_RAM_SEG_BASE))
+#define RAM(type, addr) (*((volatile type *)RAM_ADDR(addr)))
+
+void cache_ram_start(void);
+#endif
 
 #endif /* CACHE_RAM_H */

src/arch/i386/include/bitops.h

@@ -0,0 +1,20 @@
+#ifndef I386_BITOPS_H
+#define I386_BITOPS_H
+
+/**
+ * log2 - Find the truncated log base 2 of x
+ */
+
+static inline unsigned long log2(unsigned long x)
+{
+	unsigned long r = 0;
+	__asm__(
+		"bsrl %1, %0\n\t"
+		"jnz 1f\n\t"
+		"movl $-1, %0\n\t"
+		"1:\n\t"
+		: "=r" (r) : "g" (x));
+	return r;
+		
+}
+#endif /* I386_BITOPS_H */

src/arch/i386/lib/cpu_reset.inc

@@ -6,7 +6,7 @@ jmp cpu_reset_out
 
 .section ".rodata"
 
-#if ASM_CONSOLE_LOGLEVEL >= BIOS_DEBUG
+#if ASM_CONSOLE_LOGLEVEL >= BIOS_SPEW
 cpu_reset_str:		.string "cpu_reset\r\n";
 cpu_apic_str:		.string "apic: ";
 cpu_size_set_str:	.string	"cpu memory size set\r\n";
@@ -16,7 +16,7 @@ cpu_size_set_str:	.string	"cpu memory size set\r\n";
 .text
 
 __cpu_reset:
-	CONSOLE_DEBUG_TX_STRING($cpu_reset_str)
+	CONSOLE_SPEW_TX_STRING($cpu_reset_str)
 
 #ifdef SMP
 	/* Enable the local apic, and map it where we expext it */
@@ -32,15 +32,15 @@ __cpu_reset:
 	movl	(APIC_ID + APIC_DEFAULT_BASE), %edi
 	shrl	$24, %edi
 
-	CONSOLE_DEBUG_TX_STRING($cpu_apic_str)
-	CONSOLE_DEBUG_TX_HEX32(%edi)
-	CONSOLE_DEBUG_TX_CHAR($'\r')
-	CONSOLE_DEBUG_TX_CHAR($'\n')
+	CONSOLE_SPEW_TX_STRING($cpu_apic_str)
+	CONSOLE_SPEW_TX_HEX32(%edi)
+	CONSOLE_SPEW_TX_CHAR($'\r')
+	CONSOLE_SPEW_TX_CHAR($'\n')
 #endif
 
 	CALLSP(set_memory_size)
 
-	CONSOLE_DEBUG_TX_STRING($cpu_size_set_str);
+	CONSOLE_SPEW_TX_STRING($cpu_size_set_str);
 
 #ifdef SMP
 	/* Test to see if we are the boot strap processor.

src/arch/i386/lib/failover.lds

@@ -0,0 +1 @@
+	__normal_image = (ZKERNEL_START & 0xfffffff0) - 8;

src/arch/i386/lib/hardwaremain.c

@@ -49,6 +49,7 @@ static char rcsid[] = "$Id$";
 #include <part/floppy.h>
 #include <part/sizeram.h>
 #include <part/hard_reset.h>
+#include <part/fallback_boot.h>
 #include <arch/ioapic.h>
 #include <pc80/i8259.h>
 #include <pc80/keyboard.h>
@@ -289,6 +290,9 @@ void hardwaremain(int boot_complete)
 	post_code(0x96);
 	write_smp_table((void *)16, processor_map);
 
+	/* Reset to booting from this image as late as possible */
+	boot_successful();
+
 #ifdef LINUXBIOS
 	printk_info("Jumping to linuxbiosmain()...\n");
 	// we could go to argc, argv, for main but it seems like overkill.

src/arch/i386/lib/noop_failover.inc

@@ -0,0 +1,9 @@
+/* Step 1:  Test for cpu reset
+ *     That is, did I just boot or is this a later boot since power on.
+ *     The result of this test in %al
+ *     %al == 1 -- We are rebooting
+ *     %al == 0 -- This is the initial boot
+ *
+ */
+	testb	%al, %al
+	jnz	__cpu_reset

src/arch/i386/lib/pirq_routing.c

@@ -1,6 +1,7 @@
 #include <printk.h>
 #include <pci.h>
 #include <arch/pirq_routing.h>
+#include <string.h>
 
 #ifdef DEBUG
 void check_pirq_routing_table(void)

src/arch/i386/smp/start_stop.c

@@ -4,7 +4,12 @@
 #include <delay.h>
 #include <string.h>
 
-
+#ifndef START_CPU_SEG
+#define START_CPU_SEG 0x90000
+#endif
+#if (START_CPU_SEG&0xffff) != 0
+#error START_CPU_SEG must be 64k aligned
+#endif
 
 static inline void hlt(void)
 {
@@ -142,13 +147,13 @@ int start_cpu(unsigned long apicid)
 		return 0;
 	}
 
-	start_eip = 0x90000 + (((unsigned long)_start) & 0xf000);
+	start_eip = START_CPU_SEG + (((unsigned long)_start) & 0xf000);
 	if ((((unsigned long)_start) & 0xfff) != 0) {
 		printk_err("_start is not 4K aligned!\n");
 		return 0;
 	}
 	memcpy((void *)start_eip, _start, _estart - _start);
-	printk_spew("start eip=0x%08lx\n", start_eip);
+	printk_spew("start_eip=0x%08lx\n", start_eip);
        
 	num_starts = 2;
 
@@ -160,7 +165,7 @@ int start_cpu(unsigned long apicid)
 	maxlvt = 4;
 
 	for (j = 1; j <= num_starts; j++) {
-		printk_spew("Sending STARTUP #%d.\n",j);
+		printk_spew("Sending STARTUP #%d to %u.\n", j, apicid);
 		apic_read_around(APIC_SPIV);
 		apic_write(APIC_ESR, 0);
 		apic_read(APIC_ESR);