diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig index ca02e06124..4902b49a44 100644 --- a/src/mainboard/siemens/mc_rpl/Kconfig +++ b/src/mainboard/siemens/mc_rpl/Kconfig @@ -14,7 +14,6 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL select SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_RAPTORLAKE - config BOARD_SIEMENS_MC_RPL1 select BOARD_SIEMENS_BASEBOARD_MC_RPL @@ -48,10 +47,6 @@ config OVERRIDE_DEVICETREE config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_rpl.fmd" -config UART_FOR_CONSOLE - int - default 0 - config DIMM_SPD_SIZE int default 256 diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb index 20526071c9..46c8b7bbae 100644 --- a/src/mainboard/siemens/mc_rpl/devicetree.cb +++ b/src/mainboard/siemens/mc_rpl/devicetree.cb @@ -53,12 +53,6 @@ chip soc/intel/alderlake [PchSerialIoIndexGSPI3] = 0, }" - register "serial_io_uart_mode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - # Intel Common SoC Config register "common_soc_config" = "{ .gspi[1] = { @@ -166,7 +160,6 @@ chip soc/intel/alderlake end device ref crashlog off end device ref sata on end - device ref uart0 on end device ref gspi0 on end device ref p2sb on end device ref gspi1 on diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig index bee8ace103..9f2d691d0e 100644 --- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig +++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig @@ -4,5 +4,10 @@ if BOARD_SIEMENS_MC_RPL1 config BOARD_SPECIFIC_OPTIONS def_bool y + select INTEL_LPSS_UART_FOR_CONSOLE + +config UART_FOR_CONSOLE + int + default 2 endif # BOARD_SIEMENS_MC_RPL1 diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb index e6ac72007d..e95e8b8a22 100644 --- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb +++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb @@ -28,6 +28,12 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoSkipInit, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + # Intel Common SoC Config register "common_soc_config" = "{ .i2c[0] = { @@ -107,5 +113,8 @@ chip soc/intel/alderlake end end end + device ref uart0 on end + device ref uart1 on end + device ref uart2 on end end end