erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

tegra124: modify panel init sequence

Browse source 
Panel datasheet defines some delay between PWM signal out and
backlight enable. This change fixes the current sequence
and makes the delays adjustable by dt setting.

BRANCH=none
BUG=chrome-os-partner:28008
TEST=Verified on Big DVT and Nyan/Norrin panels.
     Panel works fine with dev mode, and the measurement
     of power on sequence meets panel requirements.

Change-Id: If6015bbb6015a3b203d425f5e90f676ad786b5e8
Signed-off-by: Ken Chang <kenc@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/196183
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Ken Chang 2014-04-22 12:55:00 +08:00 • committed by chrome-internal-fetch
commit 2bbcaa7281
5 changed files with 22 additions and 14 deletions
Download patch file Download diff file Expand all files Collapse all files

1
src/mainboard/google/nyan/devicetree.cb
View file

@ -47,6 +47,7 @@ chip soc/nvidia/tegra124
# various panel delay time
register "vdd_delay_ms" = "200"
register "pwm_to_bl_delay_ms" = "10"
register "vdd_to_hpd_delay_ms" = "200"
register "hpd_unplug_min_us" = "2000"
register "hpd_plug_min_us" = "250"

1
src/mainboard/google/nyan_big/devicetree.cb
View file

@ -47,6 +47,7 @@ chip soc/nvidia/tegra124
# various panel delay time
register "vdd_delay_ms" = "200"
register "pwm_to_bl_delay_ms" = "10"
register "vdd_to_hpd_delay_ms" = "200"
register "hpd_unplug_min_us" = "2000"
register "hpd_plug_min_us" = "250"

1
src/mainboard/google/nyan_blaze/devicetree.cb
View file

@ -47,6 +47,7 @@ chip soc/nvidia/tegra124
# various panel delay time
register "vdd_delay_ms" = "200"
register "pwm_to_bl_delay_ms" = "10"
register "vdd_to_hpd_delay_ms" = "200"
register "hpd_unplug_min_us" = "2000"
register "hpd_plug_min_us" = "250"

3
src/soc/nvidia/tegra124/chip.h
View file

@ -72,6 +72,9 @@ struct soc_nvidia_tegra124_config {
/* Delay before from power on asserting vdd */
int vdd_delay_ms;
/* Delay beween pwm and backlight_en_gpio is asserted */
int pwm_to_bl_delay_ms;
/* Delay before HPD high */
int vdd_to_hpd_delay_ms;

30
src/soc/nvidia/tegra124/display.c
View file

@ -252,20 +252,6 @@ void display_startup(device_t dev)
printk(BIOS_SPEW,"%s: lvds shutdown setting gpio %08x to %d\n",
__func__, config->lvds_shutdown_gpio, 0);
}
if (config->backlight_en_gpio){
gpio_output(config->backlight_en_gpio, 1);
printk(BIOS_SPEW,"%s: backlight enable setting gpio %08x to %d\n",
__func__, config->backlight_en_gpio, 1);
}
/* Set up Tegra PWM n (where n is specified in config->pwm) to drive the
* panel backlight.
*/
printk(BIOS_SPEW, "%s: enable panel backlight pwm\n", __func__);
WRITEL(((1 << NV_PWM_CSR_ENABLE_SHIFT) |
(220 << NV_PWM_CSR_PULSE_WIDTH_SHIFT) | /* 220/256 */
0x02e), /* frequency divider */
&pwm->pwm[config->pwm].csr);
if (framebuffer_size_mb == 0){
framebuffer_size_mb = ALIGN_UP(config->xres * config->yres *
@ -313,6 +299,22 @@ void display_startup(device_t dev)
update_window(disp_ctrl, config);
/* Set up Tegra PWM n (where n is specified in config->pwm) to drive the
* panel backlight.
*/
printk(BIOS_SPEW, "%s: enable panel backlight pwm\n", __func__);
WRITEL(((1 << NV_PWM_CSR_ENABLE_SHIFT) |
(220 << NV_PWM_CSR_PULSE_WIDTH_SHIFT) | /* 220/256 */
0x02e), /* frequency divider */
&pwm->pwm[config->pwm].csr);
udelay(config->pwm_to_bl_delay_ms * 1000);
if (config->backlight_en_gpio){
gpio_output(config->backlight_en_gpio, 1);
printk(BIOS_SPEW,"%s: backlight enable setting gpio %08x to %d\n",
__func__, config->backlight_en_gpio, 1);
}
printk(BIOS_INFO, "%s: display init done.\n", __func__);
/* tell depthcharge ...