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UPSTREAM: arm64: Align cache maintenance code with libpayload and ARM32

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coreboot and libpayload currently use completely different code to
perform a full cache flush on ARM64, with even different function names.
The libpayload code is closely inspired by the ARM32 version, so for the
sake of overall consistency let's sync coreboot to that. Also align a
few other cache management details to work the same way as the
corresponding ARM32 parts (such as only flushing but not invalidating
the data cache after loading a new stage, which may have a small
performance benefit).

BUG=none
BRANCH=none
TEST=none

Change-Id: I36773b526de93ec2367bc7c826e63a68bb8ef6ef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: baa3e70084
Original-Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19785
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/521024
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Julius Werner 2015-04-21 14:32:36 -07:00 • committed by chrome-bot
commit 2a9d068721
8 changed files with 93 additions and 194 deletions
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6
payloads/libpayload/arch/arm64/cache.c
View file

@ -119,7 +119,11 @@ void dcache_invalidate_by_mva(void const *addr, size_t len)
void cache_sync_instructions(void)
{
dcache_clean_all(); /* includes trailing DSB (in assembly) */
uint32_t sctlr = raw_read_sctlr_current();
if (sctlr & SCTLR_C)
dcache_clean_all(); /* includes trailing DSB (assembly) */
else if (sctlr & SCTLR_I)
dcache_clean_invalidate_all();
icache_invalidate_all(); /* includes leading DSB and trailing ISB */
}