From 2a227510f665d46125b868c7e747b619999fcf3b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 27 Mar 2017 19:02:55 +0300 Subject: [PATCH] UPSTREAM: AGESA f14: Fix memory clock register decoding Bottom five LSBs are used to store the running frequency of memory clock. BUG=none BRANCH=none TEST=none Change-Id: If241c224ecb5b5aed3e308d126cd1d7d0314417e Signed-off-by: Patrick Georgi Original-Commit-Id: e522258907c0f16fb46c8abfed64532fd3d81202 Original-Change-Id: I2dfcf1950883836499ea2ca95f9eb72ccdfb979c Original-Signed-off-by: Kysti Mlkki Original-Reviewed-on: https://review.coreboot.org/19042 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Paul Menzel Original-Reviewed-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/472718 --- src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c index ee14fed847..411caf843c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c @@ -528,7 +528,8 @@ MemMSetCSRNb ( IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); RetVal = FALSE; } - if (((Value & 0x4000) == 0) && (NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.TargetSpeed) != ((Value & 7) + 1))) { + if (((Value & 0x4000) == 0) && (NBPtr->GetMemClkFreqId (NBPtr, + NBPtr->DCTPtr->Timings.TargetSpeed) != (Value & 0x1f))) { IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: MemClk has changed\n"); RetVal = FALSE; }