diff --git a/src/soc/intel/alderlake/include/soc/cnvi.h b/src/soc/intel/alderlake/include/soc/cnvi.h
new file mode 100644
index 0000000000..7a9c30d960
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/cnvi.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ALDERLAKE_CNVI_H_
+#define _SOC_ALDERLAKE_CNVI_H_
+
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
+#define CNVI_ABORT_PLDR		0x44
+#else
+#define CNVI_ABORT_PLDR		0x80
+#endif
+
+#endif /* _SOC_ALDERLAKE_CNVI_H_ */
diff --git a/src/soc/intel/alderlake/include/soc/pcr_ids.h b/src/soc/intel/alderlake/include/soc/pcr_ids.h
index 7f0ec00f5d..3bef44fa4a 100644
--- a/src/soc/intel/alderlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/alderlake/include/soc/pcr_ids.h
@@ -20,6 +20,7 @@
 #define PID_GPIOCOM5	0x69
 
 #define PID_ESPI	0x72
+#define PID_CNVI	0x73
 #define PID_DMI		0x88
 #define PID_PSTH	0x89
 #define PID_CSME0	0x90
diff --git a/src/soc/intel/apollolake/include/soc/cnvi.h b/src/soc/intel/apollolake/include/soc/cnvi.h
new file mode 100644
index 0000000000..309c3ab0a9
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/cnvi.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_APOLLOLAKE_CNVI_H_
+#define _SOC_APOLLOLAKE_CNVI_H_
+
+#define CNVI_ABORT_PLDR		0x80
+
+#endif /* _SOC_APOLLOLAKE_CNVI_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h
index b81d700da4..7176eed973 100644
--- a/src/soc/intel/apollolake/include/soc/pcr_ids.h
+++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h
@@ -6,6 +6,7 @@
 /*
  * Port ids.
  */
+#define PID_CNVI	0x73
 #if CONFIG(SOC_INTEL_GEMINILAKE)
 #define PID_GPIO_AUDIO	0xC9
 #define PID_GPIO_SCC	0xC8
diff --git a/src/soc/intel/cannonlake/include/soc/cnvi.h b/src/soc/intel/cannonlake/include/soc/cnvi.h
new file mode 100644
index 0000000000..c847f64201
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/cnvi.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_CANNONLAKE_CNVI_H_
+#define _SOC_CANNONLAKE_CNVI_H_
+
+#define CNVI_ABORT_PLDR		0x80
+
+#endif /* _SOC_CANNONLAKE_CNVI_H_ */
diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
index f57a2efb82..3ddcaf5a9b 100644
--- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
@@ -12,6 +12,7 @@
 #define PID_GPIOCOM2	0x6c
 #define PID_GPIOCOM1	0x6d
 #define PID_GPIOCOM0	0x6e
+#define PID_CNVI	0x73
 #define PID_DMI		0x88
 #define PID_PSTH	0x89
 #define PID_CSME0	0x90
diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 2a1eadb912..743b248476 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -7,6 +7,8 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <intelblocks/cnvi.h>
+#include <soc/cnvi.h>
+#include <soc/pcr_ids.h>
 
 static const char *cnvi_wifi_acpi_name(const struct device *dev)
 {
@@ -256,7 +258,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
 				{
 					acpigen_write_store();
 					acpigen_emit_namestring("\\_SB.PCI0.PCRR");
-					acpigen_write_integer(CNVI_SIDEBAND_ID);
+					acpigen_write_integer(PID_CNVI);
 					acpigen_write_integer(CNVI_ABORT_PLDR);
 					acpigen_emit_byte(LOCAL0_OP);
 
@@ -284,7 +286,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
 						acpigen_pop_len();
 
 						acpigen_emit_namestring("\\_SB.PCI0.PCRO");
-						acpigen_write_integer(CNVI_SIDEBAND_ID);
+						acpigen_write_integer(PID_CNVI);
 						acpigen_write_integer(CNVI_ABORT_PLDR);
 						acpigen_write_integer(CNVI_ABORT_REQUEST | CNVI_ABORT_ENABLE);
 
@@ -292,7 +294,7 @@ static void cnvw_fill_ssdt(const struct device *dev)
 
 						acpigen_write_store();
 						acpigen_emit_namestring("\\_SB.PCI0.PCRR");
-						acpigen_write_integer(CNVI_SIDEBAND_ID);
+						acpigen_write_integer(PID_CNVI);
 						acpigen_write_integer(CNVI_ABORT_PLDR);
 						acpigen_emit_byte(LOCAL0_OP);
 
diff --git a/src/soc/intel/common/block/include/intelblocks/cnvi.h b/src/soc/intel/common/block/include/intelblocks/cnvi.h
index 52f9238206..c6fe131d97 100644
--- a/src/soc/intel/common/block/include/intelblocks/cnvi.h
+++ b/src/soc/intel/common/block/include/intelblocks/cnvi.h
@@ -13,22 +13,8 @@
 #define CNVI_PLDR_NOT_COMPLETE	0x03
 #define CNVI_PLDR_TIMEOUT	0x04
 
-/* CNVi PLDR Control */
-#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
-#define CNVI_ABORT_PLDR		0x44
-#else
-#define CNVI_ABORT_PLDR		0x80
-#endif
-
 #define CNVI_ABORT_ENABLE	BIT(0)
 #define CNVI_ABORT_REQUEST	BIT(1)
 #define CNVI_READY		BIT(2)
 
-/* CNVi Sideband Port ID */
-#if CONFIG(SOC_INTEL_METEORLAKE)
-#define CNVI_SIDEBAND_ID	0x29
-#else
-#define CNVI_SIDEBAND_ID	0x73
-#endif
-
 #endif	// _SOC_INTEL_COMMON_CNVI_H_
diff --git a/src/soc/intel/jasperlake/include/soc/cnvi.h b/src/soc/intel/jasperlake/include/soc/cnvi.h
new file mode 100644
index 0000000000..7c79b3cd5b
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/cnvi.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_JASPERLAKE_CNVI_H_
+#define _SOC_JASPERLAKE_CNVI_H_
+
+#define CNVI_ABORT_PLDR		0x80
+
+#endif /* _SOC_JASPERLAKE_CNVI_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/pcr_ids.h b/src/soc/intel/jasperlake/include/soc/pcr_ids.h
index c74d1f9fc3..152cedaf60 100644
--- a/src/soc/intel/jasperlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/jasperlake/include/soc/pcr_ids.h
@@ -14,6 +14,7 @@
 #define PID_GPIOCOM4	0x6a
 #define PID_GPIOCOM5	0x69
 
+#define PID_CNVI	0x73
 #define PID_DMI		0x88
 #define PID_PSTH	0x89
 #define PID_CSME0	0x90
diff --git a/src/soc/intel/meteorlake/include/soc/cnvi.h b/src/soc/intel/meteorlake/include/soc/cnvi.h
new file mode 100644
index 0000000000..90079d4c72
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/cnvi.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_METEORLAKE_CNVI_H_
+#define _SOC_METEORLAKE_CNVI_H_
+
+#if CONFIG(SOC_INTEL_METEORLAKE_S)
+#define CNVI_ABORT_PLDR		0x44
+#else
+#define CNVI_ABORT_PLDR		0x80
+#endif
+
+#endif /* _SOC_METEORLAKE_CNVI_H_ */
diff --git a/src/soc/intel/meteorlake/include/soc/pcr_ids.h b/src/soc/intel/meteorlake/include/soc/pcr_ids.h
index 1b0eda3a5d..d7e894a7ac 100644
--- a/src/soc/intel/meteorlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/meteorlake/include/soc/pcr_ids.h
@@ -16,6 +16,7 @@
 #define PID_PSF8	0x08
 #define PID_PSF7	0x07
 #define PID_PSF6	0x06
+#define PID_CNVI	0x29
 #define PID_PSF5	0x8F
 #define PID_PSF4	0xBD
 #define PID_PSF3	0xBC
diff --git a/src/soc/intel/pantherlake/include/soc/cnvi.h b/src/soc/intel/pantherlake/include/soc/cnvi.h
new file mode 100644
index 0000000000..b921f3559c
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/cnvi.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_CNVI_H_
+#define _SOC_PANTHERLAKE_CNVI_H_
+
+#define CNVI_ABORT_PLDR		0x80
+
+#endif /* _SOC_PANTHERLAKE_CNVI_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/pcr_ids.h b/src/soc/intel/pantherlake/include/soc/pcr_ids.h
index 8e655540bc..4fc5a397a0 100644
--- a/src/soc/intel/pantherlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/pantherlake/include/soc/pcr_ids.h
@@ -8,6 +8,7 @@
 #define PID_XHCI	0x09
 #define PID_DMI		0x2F
 #define PID_CSME0	0x40
+#define PID_CNVI	0x51
 #define PID_GPIOCOM0	0x59
 #define PID_GPIOCOM1	0x5A
 #define PID_GPIOCOM3	0x5B
diff --git a/src/soc/intel/tigerlake/include/soc/cnvi.h b/src/soc/intel/tigerlake/include/soc/cnvi.h
new file mode 100644
index 0000000000..ae57de3cdf
--- /dev/null
+++ b/src/soc/intel/tigerlake/include/soc/cnvi.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_TIGERLAKE_CNVI_H_
+#define _SOC_TIGERLAKE_CNVI_H_
+
+#define CNVI_ABORT_PLDR		0x80
+
+#endif /* _SOC_TIGERLAKE_CNVI_H_ */
diff --git a/src/soc/intel/tigerlake/include/soc/pcr_ids.h b/src/soc/intel/tigerlake/include/soc/pcr_ids.h
index 22f08d73d1..168a6985e8 100644
--- a/src/soc/intel/tigerlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/tigerlake/include/soc/pcr_ids.h
@@ -18,6 +18,7 @@
 #define PID_GPIOCOM4	0x6a
 #define PID_GPIOCOM5	0x69
 
+#define PID_CNVI	0x73
 #define PID_DMI		0x88
 #define PID_PSTH	0x89
 #define PID_CSME0	0x90